Silicon Image Gmbh

Rambus Inc.

Lattice Semiconductor Corporation

Dongyun Lee

Sungjoon Kim

David D Lee

Alan T Ruberg

Deog-Kyoon Jeong

Daeyun Shim

Yeshik Shin

John Hahn

Shing Kong

Edward T Pak

Mayank Gupta

Kamran Farzan

Anu Murthy

Myung Rai Cho

Hyung Rok Lee

Thomas Vogelsang

Brent Steven Haukness

Steven Cameron Woo

Ming Chu Li

Michael Raymond Miller

Paul Heninwolf

Mark D Kellam

Chieh-Yuan Chao

Bong-Joon Lee

Dae Kim

Seung-Jong Lee

Joohee Kim

Byoung Woon Kim

Sangwan Kim

Sukjae Cho

Byoung-Woon Kim

Seung-jong Lee

Seoung Jeong Lee

Edward Kim

Jen-Dong Yuh

Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

Bus distribution using multiwavelength multiplexing

Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.

Failover methods and systems in three-dimensional memory device

An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

Memory-integrated neural network

A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.

Domain-selective control component

Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.

Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream

A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.

Edge enhancement for signal transmitter

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts.

Method and apparatus to improve connection pitch in die-to-wafer bonding

A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Method and system for improving serial port memory communication latency and reliability

A system for delivering power over a network of devices connected through a serial link includes a first and second differential pairs of wires. Each differential pair of wires is double AC coupled by a HPF on one side and by another HPF on an opposite side. An LPF connects a portion of each differential pair of wires between the HPFs to a voltage source, and another LPF connects that portion of each differential pair to a load. The system further includes a third and fourth differential pairs of wires. All four differential pairs of wires are located within a single cable, such as a CAT6 cable. The first, second and third differential pair of wires are used for video links, and the fourth differential pair of wires are used for the bi-directional hybrid link. A power delivery circuit in each device includes a voltage source, a power relay switch, a signature resistor for detection, and a load detector.

Power delivery over digital interaction interface for video and audio (DiiVA)

A system may include a video link and a hybrid link that connects a transmitting device to the receiving device, and at least one intermediate hop between the transmitting device and the receiving device. The intermediate hop may be configured to relay video content from the video source to the video sink through the hybrid link using one or more data relay modes. The hybrid link may be configured to perform hybrid link control signaling (HLCS) to manage a physical layer of the hybrid link. The video link between the video source and the video sink may be configured to transmit a video stream the from video source to the video sink over one or more video lanes. A video link training may be implemented for the video link and the hybrid link.

Video management and control in home multimedia network

A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

Bi-directional digital interface for video and audio (DIVA)

Growing community of inventors

San Jose, CA, United States of America

Dongyun Lee