Yangtze Memory Technologies Co., Ltd.

Dongxue Zhao

Zhiliang Xia

Zongliang Huo

Tao Yang

Yuancheng Yang

Wenxi Zhou

Kun Zhang

Lei Liu

Di Wang

In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

Memory devices having vertical transistors and methods for forming the same

In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

Vertical memory devices and methods for operating the same

In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.

Memory devices having vertical transistors and stacked storage units and methods for forming the same

In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.

Growing community of inventors

Wuhan, China

Dongxue Zhao