Samsung Electronics Co., Ltd.

Dongsuk Shin

Dong Hyuk Kim

Hoi Sung Chung

Myungsun Kim

Pankwi Park

Sangmoon Lee

Seokhoon Kim

Naein Lee

Ki Hwan Kim

Jinbum Kim

Jin-Wook Kim

Woo Bin Song

Junggun You

Hyun-Kwan Yu

Yihwan Kim

Junghun Heo

Seung Ryul Lee

Youngduk Kim

Gigwan Park

Joonseok Kim

Dongwon Kim

Donghyun Roh

Myunggil Kang

Dong Chan Suh

Keunhwi Cho

Jinyeong Joe

Minhee Choi

Chulwoong Lee

Dahye Kim

Sujin Jung

Jung Nyoung Heo

Chanjin Park

Bonyoung Koo

Jungtaek Kim

Byeongchan Lee

Namkyu Cho

Keum Seok Park

Hongsik Yoon

Sahwan Hong

Sungyoung Lee

Seongjin Nam

Ingyu Jang

Jungho Yoo

Kooktae Kim

Youngdal Lim

Sunyoung Lee

Dongwoo Kim

Seung Hun Lee

Yoosang Hwang

Nae-in Lee

Kiseok Lee

Hui-Jung Kim

Jiyoung Kim

Wandon Kim

Gyeom Kim

Dongsoo Lee

Hanjin Lim

Sunguk Jang

Choeun Lee

Yang Xu

Yunhyeok Im

Ryong Ha

Sanggil Lee

Taehyun An

Doyoung Choi

Ji Hoon Cha

Jeongho Yoo

Sungkeun Lim

Dongchan Suh

Jeongmin Lee

Hokyun An

Joongchan Shin

Hyungeun Choi

Suyoung Bae

Juyeon Kim

Chan Min Lee

Eunju Cho

Byungsu Kim

Moonhan Park

Dohyun Go

Woonki Shin

Hosung Son

YongJoo Lee

Kyungyeon Hwang

Jaeseoung Park

Inhwan Baek

A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

Semiconductor device including a vertically stacked channel pattern and method for manufacturing the same

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

Semiconductor device and method of fabricating the same

A semiconductor device includes: an active region extending on a substrate in a first direction; a gate structure intersecting the active region and extending on the substrate in a second direction; and a source/drain region on the active region on at least one side of the gate structure. The source/drain region may include a first epitaxial layer on the active region and including impurities of a first conductivity type in a first concentration, a second epitaxial layer on the first epitaxial layer and including the impurities of the first conductivity type in a second concentration, and a first barrier layer between the first epitaxial layer and the second epitaxial layer, wherein the first barrier layer includes doped oxygen.

Source/drain region of a semiconductor device having an oxygen doped barrier layer formed between first and second epitaxial layers

A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

Multi-channel field effect transistors with enhanced multi-layered source/drain regions

A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.

Semiconductor device and method of manufacturing the same

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

Integrated circuit device

A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

Semiconductor transistor device including multiple channel layers with different materials

A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

Semiconductor including active contact buried portions

Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

Multi-oxide-semiconductor field-effect transistor with stacked source/drain structure

A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Semiconductor device

A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

Power management integrated circuit, power management method, mobile device and clock adjusting method

The present disclosure provides a device and methods to control a temperature of an integrated circuit (IC). For example, a device may include a circuit (e.g., an IC), a power monitor, a temperature sensor, and a controller. In some examples, temperature may be estimated based on power measured by a dynamic power monitor (DPM). In some cases, the estimated temperatures may be corrected based on temperature sensed by a temperature sensor on the IC. The power may be measured in shorter time periods and/or more frequent time periods compared to a time periods that the temperature sensor senses temperature. Accordingly, the temperature of an IC may be detected and adjusted more frequently based on the power measurements, and the temperature estimates may be adjusted for accuracy based on sensed temperatures.

Method and device for temperature detection and thermal management based on power measurement

An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

Integrated circuit devices

A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.

Growing community of inventors

Yongin-si, South Korea

Dongsuk Shin