Semiconductor Components Industries, LLC

Dongsoo Kim

Kwangbo Cho

Isao Takayanagi

Chiajen Lee

Taehee Cho

Ashirwad Bahukhandi

Kwang-bo Cho

Jae Eun Lim

Sungkuk Hong

Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry and column power control circuitry that selectively enables or disables the column readout circuitry for various column lines. The column power control circuitry and the column readout circuitry may be coupled to column decoder circuitry. The column decoder circuitry may provide a column address signals to the power control and the readout circuitry. The power control circuitry may enable only column lines for which column addresses have been received.

Imaging systems with switchable column power control

Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.

Ramp and successive approximation register analog to digital conversion methods, systems and apparatus

An image sensor may include an array of image pixels arranged according to a predetermined pattern. A 3-by-3 pixel sub-sampling method is provided that supports a high-speed sub-resolution video mode. The 3-by-3 sub-sampling method may involve organizing the image pixel array into groups, each of which contains a 3-by-3 array of nine pixels. Image pixels at the four corners of each group may be sampled and combined to form a final output. Final outputs produced from each group may form a sub-sampled array that is used by the sub-resolution video mode.

Image sensors with pixel array sub-sampling capabilities

An imaging system may be provided with a backside illuminated pixel array that includes imaging pixels and rows of auto-focus pixels. The imaging pixels may generate image data and the auto-focus pixels may generate application-specific data. The imaging pixels may be provided with an array of color filters. The auto-focus pixels may be provided with rows of color filters that are offset with respect to the imaging pixel color filters. The auto-focus pixel color filters may include clear color filters and opaque color filters for blocking image light received at selected incident angles. The system may include an adjustable lens that focuses light onto the pixel array. The pixel array may be coupled to processing circuitry that determines whether an image is focused based on the application-specific data and may adjust the lens in response to determining that the image is not focused.

Backside illuminated imaging systems having auto-focus pixels

Electronic devices may have camera modules that include an image sensor and processing circuitry. An image sensor may include a pixel array having pixel rows and pixel columns. The image pixels in a pixel row may include long-integration pixels and short-integration pixels. Row control signal lines for each pixel row may include a row-select control line, a reset control line, and two transfer control lines or may include a row-select control line, two reset control lines, and a transfer control line. Row control circuitry may be used to operate the pixel array to capture a column-interleaved image with short-exposure pixel values and long-exposure pixel values interleaved in a column-based pattern. The column-interleaved image may be used to form an interpolated short-exposure image and an interpolated long-exposure image from which a column-based interleaved high-dynamic-range image is generated.

Column-based high dynamic range imaging systems

Electronic devices may include time-of-flight image pixels. A time-of-flight image pixel may include first and second charge storage regions coupled to a photosensor and a transfer transistor with a gate terminal coupled to the first storage region. An electronic device may further include a light pulse emitter configured to emit pulses of light to be reflected by objects in a scene. Reflected portions of the emitted pulses of light may be captured along with background light by the time-of-flight image pixels. Time-of-flight image pixels may be configured sense the time-of-flight of the reflected portions of the emitted pulses. The electronic device may include processing circuitry configured to use the sensed time-of-flight of the reflected portions to generate depth images of a scene. Depth images may include depth-image pixel values that contain information corresponding to the distance of the objects in the scene from the electronic device.

Time-of-flight imaging systems

Imaging systems may include camera modules that include an array of image sensors. An image sensor may include multiple image pixel arrays arranged in rows and columns, multiple control circuits for operating the image pixels of that image sensor, and shared readout circuitry for reading out the image pixels of the image pixel arrays of that image sensor. Each control circuit may be operable to select rows of image pixels that extend across a row of image pixel arrays. Shared readout circuitry may include one or more line buffers configured to temporarily store image data captured by image pixels in the selected rows of image pixels. Shared readout circuitry may include selection circuitry configured to readout image data from groups of associated pixels located in separate image pixel arrays. An imaging system may include processing circuitry for processing the image data from each group of pixels.

Method and apparatus for array camera pixel readout

Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to column readout circuitry through column randomizing circuitry. The column readout circuitry may include a column circuit associated with each pixel column and at least one reserve column circuit. The column randomizing circuitry may randomize the distribution of image signals from the pixel columns to the column readout circuitry. The column randomizing circuitry may distribute the randomized image signals from at least one of the pixel columns to a reserve column circuit when any of the column circuits associated with the pixel columns has failed. The column randomizing circuitry may include an output column line for each column circuit and first and second transistors coupled in parallel to each output column line.

Image sensors with column failure correction circuitry

A system for correcting a column line failure in an imager includes a pixel selection circuit configured to receive three adjacent pixel output signals, P(n&#x2212;1), P(n) and P(n+1), respectively, from three adjacent column lines, (n&#x2212;1)column line, ncolumn line and (n+1)column line. The (n&#x2212;1)column line is disposed left of an ncolumn line, and the (n+1)column line is disposed right of the ncolumn line. A generator for generating a bit pattern is also included for indicating a column line failure in the three adjacent column lines. The pixel selection circuit is configured to provide a pixel output signal from one of the three adjacent column lines, based on the bit pattern.

CMOS image sensor with built in correction for column failure

Apparatus and a method for correlated double sampling using an up-counter for parallel image sensors. All bits of a counter are set to one. An offset signal is compared to a first reference signal to define a first period during which the counter is incremented. After the first period, all bits of the counter are inverted. A sensor signal is compared to a second reference signal to define a second period during which the counter is incremented to generate a correlated double sampling value.

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San Jose, CA, United States of America

Dongsoo Kim