Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Dongsoo Kang

Jun Hee Yoo

Sung Hyun Lee

Jaeyoun Youn

Hyojin Choi

Sua Kim

Il Han Park

Hak-soo Yu

Chulwoo Park

Bub-chul Jeong

Hyunseok Seo

Eun-jin Ryu

Byungkeol Choi

Jaegeun Yun

Sungmok Hwang

Jinyoung Park

Kyoung-june Min

Euicheol Lim

Haksoo Yu

Jinsu Jung

Jong-myon Kim

Jaeboong Lee

Jeongha Kim

Kiyeon Lee

A test element group (TEG) disposed adjacent to at least one memory chip on a wafer includes a ring oscillator configured to output a clock signal based on a direct current (DC) signal received through a first pad and from a test device, a first divider configured to divide the clock signal and to output a first divided signal, and a sequential circuit set configured to receive the clock signal and the first divided signal, to generate a test signal based on the clock signal and the first divided signal, and to output the test signal to the test device through a second pad. The sequential circuit set includes a sequential circuit having a configuration corresponding to at least one circuit included in the at least one die.

Test element group and test method

A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

System interconnect and operating method of system interconnect

A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Test method of semiconductor memory device and semiconductor memory system transferring fail address data from a volatile to a non-volatile memory array using an error-correction code engine

A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

Semiconductor devices including application processor connected to high-bandwidth memory and low-bandwidth memory, and channel interleaving method thereof

A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

DRAM controller having DRAM bad page management function and bad page management method thereof

Provided is a method for converting a first image signal expressed in a first color space into a second image signal expressed in a second color space on a subword parallelism basis. The method includes determining a first image parameter of a second image signal matrix as a function calculated by multiplying conversion coefficients of a first row constituting an image conversion matrix by image parameters constituting a first image signal matrix; determining a second image parameter of the second image signal matrix as a function expressed by at least one of image parameters constituting the first image signal matrix and the determined first image parameter of the second image signal matrix; determining a third image parameter of the second image signal matrix as a function expressed by at least one image parameter unused for determining the second image parameter of the second image signal matrix among the image parameters constituting the first image signal matrix, and by the determined first image parameter of the second image signal matrix; and finally calculating the second image signal matrix by shifting the determined image parameters constituting the second image signal matrix by a predetermined number of bits.

Method for converting color space of image signal

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Hwaseong-si, South Korea

Dongsoo Kang