Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Dongryeol Oh

Michael Choi

Youngjae Cho

Kyoungjun Moon

Kyoungho Kim

Younghyo Park

Seungtak Ryu

An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.

Analog-to-digital converter

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n&#x2212;1)differential signal pairs among n differential signal pairs, in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs, and sequentially generate each of n upper differential data pairs to be used as n-bit upper digital data, in response to a respective one of the sequentially-generated n first differential data pairs. The first analog-digital conversion unit is further configured to, during a second analog-digital conversion operation, simultaneously discharge each of the n first differential node pairs, in response to a ndifferential signal pair among the n differential signal pairs.

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Suwon-si, South Korea

Dongryeol Oh