Alibaba Group Holding Limited

C-sky Microsystems Co., Ltd.

Dongqi Liu

Chen Chen

Lei Huang

Chang Liu

Chaojun Zhao

Yimin Lu

Dingyan Wei

Haowen Chen

Zhao Jiang

Wenjian Xu

The embodiments of the present application provide a processing unit. The processing unit comprises: an instruction fetching unit configured for fusing instruction of vector configuration instruction and vector operation instruction that are adjacent in order to obtain fusion instruction; an instruction decoding unit configured to decode the fusion instruction to obtain first execution information and second execution information; a vector configuration unit configured to execute the vector configuration instruction according to the first execution information, modify vector control register, and bypass the value of the modified vector control register to the vector operation unit; the vector operation unit configured to execute the vector operation instruction according to the second execution information and the value of the modified vector control register.

Computing device and method for fusing and executing vector instructions

An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information. The instruction processing apparatus selectively enables an access channel of the instruction cache based on the path prediction information by using the access control unit, to reduce dynamic power consumption in access. A corresponding path prediction method, a computer system, and a system-on-chip are also disclosed.

Path prediction method used for instruction cache, access control unit, and instruction processing apparatus

An instruction processing device and an instruction processing method are provided. The instruction processing device includes: a first-level branch target buffer, configured to store entries of a first plurality of branch instructions; a second-level branch target buffer, configured to store entries of a second plurality of branch instructions, wherein the entries in the first-level branch target buffer are accessed faster than the entries in the second-level branch target buffer; an instruction fetch unit coupled to the first-level branch target buffer and the second-level branch target buffer, the instruction fetch unit including circuitry configured to add, for a first branch instruction, one or more entries corresponding to the first branch instruction into the first-level branch target buffer when the one or more entries corresponding to the first branch instruction are identified in the second-level branch target buffer; and an execution unit including circuitry configured to execute the first branch instruction.

Moving entries between multiple levels of a branch predictor based on a performance loss resulting from fewer than a pre-set number of instructions being stored in an instruction cache register

An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

System, device, and method for obtaining instructions from a variable-length instruction set

A processor comprises a trusted execution environment and a non-trusted execution environment. The processor further comprises a common resource accessible in both the trusted execution environment and the non-trusted execution environment and an instruction processing device including circuitry configured to fetch an instruction for decoding and execute the decoded instruction. The instruction processing device includes circuitry further configured to determine consistency between a current execution environment of the processor and a resource status in response to a result from instruction decoding indicating that instruction involves access to the common resource, and load content corresponding to the current execution environment into the common resource in response to a determination that the current execution environment is inconsistent with the resource status, wherein the resource status indicates an execution environment corresponding to content in the common resource. A corresponding instruction execution method in the processor is also disclosed.

Processor and instruction execution method

A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent. In the execution unit, the memory access instructions are executed according to the send order. This helps avoiding re-execution of a memory access instruction due to an address correlation of the memory access instruction. Consequently, this eliminates the need of adding an idle cycle in an instruction pipeline and the need of refreshing the pipeline to clear a memory access instruction that is incorrectly speculated.

Growing community of inventors

Hangzhou, China

Dongqi Liu