Samsung Electronics Co., Ltd.

Dongoh Kim

Kiseok Lee

Chan-Sic Yoon

Yoosang Hwang

Doosan Back

Gyuhyun Kil

Keunnam Kim

Sunghee Han

Jemin Park

Bong-Soo Kim

Jung-Hoon Han

Junghoon Han

Myeong-Dong Lee

Bongsoo Kim

Hyeonok Jung

Hyosub Kim

Euna Kim

Chansic Yoon

Dongchan Lee

Youngchan Lee

Jiseok Jung

Minwoo Cha

Yoongoo Han

Hui-Jung Kim

Sungho Jang

Augustin Jinwoo Hong

Hoin Lee

Kiwook Jung

Sunghak Cho

Daewon Kim

Kyunghwan Lee

Yongseok Kim

Min Hee Cho

Sangwoo Lee

Eun Ah Kim

Taejin Park

Sohyun Park

Seokhan Park

Hyo-Sub Kim

Chulkwon Park

Sungsu Kim

Woosong Ahn

Eun-ji Yong

Jongpil Seo

A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

Semiconductor devices

An image sensor includes a pixel unit including a plurality of pixels, and configured to generate an analog signal using the plurality of pixels, a data converter configured to receive the analog signal and convert the analog signal into a digital signal, and at least one processor configured to generate image data by performing crosstalk correction and remosaic on the digital signal, output the image data to an external device, receive image data information from the external device, determine a saturation ratio based on the image data information, and adjust settings of the remosaic based on the saturation ratio.

Image sensor correcting crosstalk, operating method of image sensor, and electronic device including image sensor

A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Semiconductor device

A display apparatus including a housing, a display module arranged inside the housing to display an image, a printed circuit board (PCB) connected to a plurality of cables provided to be electrically connected to the display module, a board case having a receiving space formed within the board case, the receiving space accommodating the PCB, and a cable clamp arranged on the board case to close a side of the receiving space, wherein the cable clamp includes a body, a first cut which is cut from a side of the body, a plurality of second cuts branched from an end of the first cut, and a plurality of through holes formed at one ends of the plurality of second cuts and passing through the body, each through hole having one of the plurality of cables inserted to and coupled with the through hole.

Board case and display apparatus including the same

A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

Semiconductor and manufacturing method of the same

A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.

Semiconductor memory device

A display apparatus including a sealing member having an improved structure, the display apparatus includes a housing including an opening, a display module including a display panel, the display module arranged inside the housing for the image to be displayed through the opening, a housing cover coupled to the housing to cover the opening while covering a rear surface of the display module, and a sealing member provided to seal a gap between the housing and the housing cover, the sealing member including a contact surface convexly formed toward the housing cover and a first protrusion and a second protrusion arranged on the contact surface, wherein at least a portion of the contact surface located between the first protrusion and the second protrusion is located at a same level as the first protrusion and the second protrusion or protrudes outward of the first protrusion and the second protrusion.

Display apparatus

A semiconductor device includes a substrate having a first region and a second region. A device isolation layer is disposed in the substrate between the first region and the second region. The device isolation layer includes a buried dielectric layer in a trench that is recessed from a top surface of the substrate. A first liner layer is between the trench and the buried dielectric layer. A semiconductor layer is disposed on a top surface of the substrate of the first region. A first gate pattern is disposed on the semiconductor layer. A protrusion is disposed on a top surface of the device isolation layer.

A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

Semiconductor device and manufacturing method of the same

A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

Semiconductor memory device and method of fabricating the same

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

Growing community of inventors

Daegu, South Korea

Dongoh Kim