Montage Technology Co., Ltd.

Integrated Device Technology, Inc.

Dongming Lou

Weidong Fan

Yong Wang

Xin Liu

Zhongyuan Chang

Pengfei Hu

Junqiang Shang

Ronghui Chen

Meng Mei

A test circuit includes a signal processor, a first resistor, a second resistor, a first switch, and a second switch. The signal processor is coupled to a first drive end, a second drive end, a first sensing end, and a second sensing end. The first resistor is coupled between the first drive end and the first sensing end. The second resistor is coupled between the second drive end and the second sensing end. The first switch is coupled between the first sensing end and a first end of a device under test. The second switch is coupled between the second sensing end and a second end of the device under test. The first drive end is coupled to the first end of the device through a first transmission wire, and the second drive end is coupled to the second end of the device through a second transmission wire.

Test circuit and test apparatus comprising the test circuit

The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

Method for calibrating channel delay skew of automatic test equipment

A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.

Method for measuring phase locked loop bandwidth parameters for high-speed serial links

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Shanghai, China

Dongming Lou