Samsung Electronics Co., Ltd.

Hyundai Motor Company

Dongmin Shin

Jinyoung Kim

Sehwan Park

Youngdeok Seo

Hongrak Son

Youngjun Hwang

Injoo Kim

Ilhan Park

Geunyeong Yu

Bohwan Jun

Kyongsu Kim

Sukhoon Song

Jinwoo Jung

Youngjun Cho

Yoonjae Lee

Joonsuc Jang

Dongryul Shin

Jiyoup Kim

Wijik Lee

Woosik Cho

Kyunggu Kim

Sungmin Joe

Taewook Ham

Hongpyo Bae

Handug Lee

Sigwan Kim

Heeyoul Kwak

Hyelee Song

Weonjai Choi

Yoondo Lee

Shin Hyoung Kim

Minji Kim

Junjin Kong

Myungkyu Lee

Sanghyuk Park

Kwanwoo Noh

Seonghyeog Choi

Hyong Joon Park

Jung Hong Joo

Beom Kyu Shin

Woohyun Kang

Junpyo Hong

Kiyong Lee

Kangseok Lee

Junho Shin

Jaehun Jang

Youngsik Moon

Joon Hwan Kim

Jinhee Kim

Daeyeol Yang

Yeonkyu Jeong

Wooyong Jeon

Jeayun So

Soonyoung Kang

Hyeonjong Song

Sangsik Yoon

Jaehoon Yoon

In Pil Yoo

Kijun Jeon

Kyoungbin Park

Hwan Chang

Younghwi Yang

Jusang Lee

Shinho Oh

Heesuk Yoon

Hankyeol Kim

Minki Song

Sungjun Yoon

Junu Hong

An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

Encoder and encoding method

An example memory system includes a memory device and a memory controller. The memory device is configured to read, from a memory cell array, hard decision data based on a hard read voltage and first soft decision data based on first soft read voltages obtained based on the hard read voltage and a first voltage offset, generate a first compressed sub-segment based on encoding a position of a bit having a first value into a position value for each of first soft decision sub-segments in the first soft decision data, and output first compressed data including first compressed sub-segments. The memory controller is configured to receive the first compressed data, count the number of position values in each of the first compressed sub-segments, and provide, to the memory device based on the counted number, a command to request a change of a voltage offset and a recompression operation.

Memory controller, operation method thereof, and memory system

A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

Memory device that performs erase operation to preserve data reliability

A method of transmitting data in a storage device includes encrypting original data based on a homomorphic encryption algorithm to generate encrypted data, generating a parameter for regeneration of a ciphertext higher than an operation level of the encrypted data by using the encrypted data and a key value, and transmitting the encrypted data and the parameter to an external host device.

Storage device, host device and data transfer method thereof

In embodiments, an electronic device may include a housing having an inner space, a printed circuit board (PCB) disposed in the inner space of the housing, a first antenna structure disposed at a position spaced apart from the PCB, and transmitting and/or receiving a radio signal in a first frequency band, at least one second antenna structure disposed at a position spaced apart from the PCB, and transmitting and/or receiving a radio signal in a second frequency band different from the first frequency band, and a flexible substrate electrically connecting the PCB and the first antenna structure. The flexible substrate may include a first connecting portion electrically connected to the PCB, an interconnecting portion extended from the first connecting portion to the first antenna structure, at least one branch portion branched from at least a part of the interconnecting portion, and extended to the at least one second antenna structure, at least one first conductive path disposed in the interconnecting portion, and electrically connecting the first connecting portion and the first antenna structure, and at least one second conductive path disposed in the interconnecting portion and the at least one branch portion, and electrically connecting the first connecting portion and the at least one second antenna structure.

Antenna and electronic device including same

A cleaning robot capable of entering a region under an obstacle and cleaning by reducing a height of a LiDAR sensor, and a control method thereof are provided. The cleaning robot includes a main body, a driving device, a cleaning device, a LiDAR sensor and configured to be raisable and lowerable between a first position and a second position having different heights, a bumper sensor configured to detect a collision between the LiDAR sensor and an obstacle, an obstacle sensor configured to obtain information on an obstacle, and a processor configured to generate a cleaning map based on an output of the LiDAR sensor and an output of the obstacle sensor, and control the sensor driver to adjust a height of the LiDAR sensor based on at least one of the cleaning map, an output of the bumper sensor, or the output of the obstacle sensor.

Cleaning robot and control method thereof

Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

Memory controller calculating optimal read level, memory system including the same, and operating method of memory controller

A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

Non-volatile memory device, controller for controlling the same, storage device having the same, and reading method thereof

Provided are a cleaning robot for obtaining a map of an indoor space, and an operating method thereof. The cleaning robot may: search the indoor space at a first location of the cleaning robot by using at least one sensor; obtain a grid map including a searched area, which has been searched at the first location, and at least one unsearched area, which has not been searched at the first location; determine, as a travel destination, a first unsearched area among the at least one unsearched area based at least in part on a distance from the first location; obtain area information including at least one of geometry information, structure information, or obstacle information about the first unsearched area while moving the cleaning robot to the determined first unsearched area; and update the grid map by using the obtained area information.

Cleaning robot capable of obtaining map of indoor space and operating method thereof

Antenna and electronic device including the same

A robot vacuum cleaner is provided. The robot vacuum cleaner includes a camera, a memory configured to store an artificial intelligence model trained to identify an image from an input image and shape information corresponding to each of a plurality of objects, and a processor configured to control the electronic apparatus by being connected to the camera and the memory, wherein the processor is configured to input an image obtained by the camera to the artificial intelligence model to identify an object included in the image, obtain shape information corresponding to the identified object among the plurality of shape information stored in the memory, and set a traveling path of the robot vacuum cleaner based on the shape information and size information related to the object.

Electronic apparatus and method of controlling thereof

A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

Storage devices and methods of operating storage devices

A method of operating a nonvolatile memory device is provided. The method includes: dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups; generating time-difference information including a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups; generating offset information including a plurality of offset values corresponding to differences between a plurality of default read voltages and a plurality of corrected read voltages; generating compensated read voltages corresponding to a read address based on the offset information and the time-difference information; and performing a read operation to read data from the nonvolatile memory device based on the read address and the compensated read voltages.

Storage device including nonvolatile memory device and method of operating the same

A nonvolatile memory device includes; a memory cell array including a meta data region storing chip-level information, control logic identifying a target cell in response to a command, machine learning (ML) logic inferring an optimum parameter based on the chip-level information and physical information associated with the target cell applied as inputs to an artificial neural network model, and a buffer memory configured to store weight parameters of the artificial neural network model.

Nonvolatile memory device including artificial neural network, memory system including same, and operating method of nonvolatile memory device including artificial neural network

Growing community of inventors

Seoul, South Korea

Dongmin Shin