Qualcomm Incorporated

Dongmin Park

Yiwu Tang

Lai Kan Leung

Jong Min Park

Yue Chao

Yunliang Zhu

Jafar Savoj

Masoud Moslehi Bajestan

Tomas O'Sullivan

Jianjun Yu

Alvin Siu-Chi Li

Li Liu

Beomsup Kim

Jingcheng Zhuang

Mustafa Keskin

Dongling Pan

Marco Zanuso

Sujiang Rong

Giovanni Marucci

Shilei Hao

Heui In Yoon

Younghyun Lim

A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

Phase interpolation-based fractional-N sampling phase-locked loop

A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.

Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection

A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

Prescaler for a frequency divider

Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

Ring oscillator based frequency divider

In certain aspects, a sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference-voltage circuit coupled to the sampling capacitor. The reference-voltage circuit is configured to generate a reference voltage based on a supply voltage, and generate a voltage difference between a voltage on the sampling capacitor and the reference voltage.

Sampling phase-locked loop

A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

Frequency synthesizer with selectable modes

A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

System and method for maintaining local oscillator (LO) phase continuity

A method and system for self-powering a clock input buffer is disclosed. The system includes an input node adapted to receive an alternating current (AC) signal having an instantaneous voltage oscillating between a minimum voltage and a maximum voltage. The system includes a pass transistor having a voltage controlled terminal, a first transfer terminal, and a second transfer terminal. The first transfer terminal connects to the input node and the second transfer terminal connects to a power node. The circuit also includes a plurality of transistors adapted to form a logic gate connected to the power node, and having a sensing terminal connected to the input node and an output terminal connected to the voltage controlled terminal. The logic gate produces a control voltage on the output terminal in response to an input voltage on the sensing terminal. The circuit also includes an energy-storage element having a first terminal connected to the power node.

Self-powered clock input buffer

Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.

Sampling phase-locked loop (PLL)

An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.

Digital duty cycle correction for frequency multiplier

An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.

Charge pump with switching gate bias

An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

Self-biased charge pump

A local oscillator communicates a signal of relatively low frequency across an integrated circuit to the location of a mixer. Near the mixer, a frequency-multiplying SubHarmonically Injection-Locked Oscillator (SHILO) receives the signal and generates therefrom a higher frequency signal. If the SHILO outputs I and Q quadrature signals, then the I and Q signals drive the mixer. If the SHILO does not generate quadrature signals, then a quadrature generating circuit receives the SHILO output signal and generates therefrom I and Q signals that drive the mixer. In one advantageous aspect, the frequency of the signal communicated over distance from the local oscillator to the SHILO is lower than the frequency of the I and Q signals that drive the mixer locally. Reducing the frequency of the signal communicated over distance can reduce power consumption of the LO signal distribution system by more than fifty percent as compared to conventional systems.

Low power LO distribution using a frequency-multiplying subharmonically injection-locked oscillator

A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

Current-mode buffer with output swing detector for high frequency clock interconnect

A serial bit stream having a given bit per second rate is received and distributed to a plurality of phase shifted samplers. A multi-phase sampling trigger is generated at a rate lower than the given bit per second rate, and each of the phase shifted samplers is controlled by one of the phases of the multi-phase sampling trigger. The time spacing between phases of the multi-phase sampling trigger is the inverse of the given bit per second rate. The phase of the multi-phase sampling trigger is aligned with the phase of the serial bit, to collectively recover by the plurality of phase shifted samplers a plurality of consecutive bits from the serial bit stream.

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San Diego, CA, United States of America

Dongmin Park