Lg Electronics Inc.

Samsung Electronics Co., Ltd.

Yonsei University

Dongkyu Kim

Sangrim Lee

Kwangseok Noh

Hojae Lee

Hyunsoo Ko

Kukheon Choi

Myeongjin Kim

Seokhyun Lee

Minjung Kim

Yunjung Yi

Jaehoon Chung

Hyeonjeong Hwang

Jaegwon Jang

Kilbom Lee

Kyoung Lim Suk

Yeonho Jang

Seungmin Lee

Donghyun Lee

Gwangjae Jeon

Byung-Wook Min

Bonghoe Kim

Ilmu Byun

Jongyoun Kim

Taewon Yoo

Kyounglim Suk

Hanbyul Seo

Jiwon Kang

Sukhyon Yoon

Heejin Kim

KiTae Kim

Kyutae Park

Jongwoong Shin

Sooyong Choi

Daesik Hong

Keung Beum Kim

Sangjoon Park

Kyungsik Min

Seungyun Lee

Haesoon Lee

Younghoon Kwak

Kijun Kim

Hyukjin Chae

Inkwon Seo

Jinmin Kim

Hyunho Lee

Kwangpyo Choi

Woochan Kim

Hyunseok Kim

Youngo Park

Sangwon Lee

Jung-Ho Park

Jungmin Lee

Woonghee Lee

Sangwook Han

Gwanmo Ku

Kijun Jeon

Wonjae Lee

Jungho Park

Daeho Lee

MinJung Kim

Seokkyu Choi

Sangwook Baek

Jaeyeong Choi

Yu-Jeong Jeon

Gihyeon Bae

Taekeun Kang

Seunglae Kam

Sang-Hyen Park

A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

Semiconductor package

A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.

Semiconductor package including redistribution substrate and method of manufacturing the same

A redistribution substrate may include a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first and second dummy patterns being in the first insulating pattern, and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal and power/ground patterns being in the second insulating pattern. The first dummy pattern may be located below the signal pattern, and the second dummy pattern may be located below the power/ground pattern. The first dummy pattern may include dot patterns, and the second dummy pattern may include a plate pattern.

Redistribution substrate and semiconductor package including the same

A semiconductor package includes: a package substrate; a first semiconductor chip disposed on the package substrate; a heat-dissipation pattern disposed on the first semiconductor chip; a first mold layer disposed on the package substrate and at least partially surrounding the first semiconductor chip and the heat-dissipation pattern; a redistribution layer disposed on the first mold layer; a penetration electrode penetrating the first mold layer and coupled to the package substrate; and a connection pattern disposed on the penetration electrode, and connecting the redistribution layer to the penetration electrode, wherein a top surface of the heat-dissipation pattern and a top surface of the connection pattern are exposed by the first mold layer.

Semiconductor package and method of fabricating the same

An antenna device comprises: a first antenna; a second antenna; and a plurality of single decoupling network circuits DN_-DN_n which electromagnetically connect the first antenna and second antenna and remove a self-interference signal, wherein a multi-stage decoupling network circuit in which the DN_-DN_n are dependent-connected can be configured such that a Yparameter of the multi-stage decoupling network circuit becomes equal to or lower than a predetermined value on frequencies f_-f_n, respectively.

Antenna device having multi-stage decoupling network circuit

A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

Semiconductor package including redistribution substrate

A semiconductor package includes a redistribution substrate including a first surface and a second surface that are opposite to each other, an antenna substrate on the first surface and including a first insulating portion and antenna patterns on a top surface of the first insulating portion, and a first semiconductor chip on the second surface. The redistribution substrate includes a second insulating portion, and a redistribution pattern in the second insulating portion. The redistribution pattern includes an interconnection portion extending parallel to a top surface of the second insulating portion, and a via portion protruding from the interconnection portion toward the first surface. A width of the via portion decreases as a height in a direction from the second surface toward the first surface increases. The active surface of the first semiconductor chip is adjacent to the second surface.

A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

Semiconductor package including outer conductive plate

A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.

A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.

A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

Semiconductor package including a dummy pattern

An image processing apparatus for performing image quality processing on an image includes: a memory configured to store one or more instructions; and a processor configured to execute the one or more instructions stored in the memory to: obtain a first image by downscaling an input image by using a downscale network; extract first feature information corresponding to the first image by using a feature extraction network; obtain a second image by performing image quality processing on the first image based on the first feature information, by using an image quality processing network; and obtain an output image by upscaling the second image, extracting second feature information corresponding to the input image, and performing image quality processing on the upscaled second image based on the second feature information, by using an upscale network.

Image processing apparatus and operating method thereof

Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

Growing community of inventors

Seoul, South Korea

Dongkyu Kim