Samsung Electronics Co., Ltd.

Dongjin Jung

Hyeoungwon Seo

Ilgweon Kim

Junhwa Oh

Jungwoo Seo

Chanju Park

Junkwon Choi

Jooyoung Lee

Sangkyu Kang

Daehyun Moon

Kyuchun Han

Sanghyuk Wi

Jungi Jeong

Taeksun Kwon

The disclosure relates to a fifth generation (5G) or a sixth generation (6G) communication system for supporting a higher data transfer rate. A dual polarization patch antenna structure and an electronic device including same are provided.

Antenna structure and electronic device including same

An antenna module, according to various embodiments, may comprise: a first layer including a first etching region, a first via pad disposed to be spaced apart from an edge of the first etching region, and a first via hole disposed on one surface of the first via pad; and a second layer stacked on one surface of the first layer, and including a second etching region, a plurality of second via pads disposed to be spaced apart from an edge of the second etching region, a plurality of second via holes disposed on one surface of the plurality of second via pads, and a plurality of second dividing lines electrically connecting the plurality of second via pads.

Antenna module and electronic device comprising same

An electronic apparatus is provided. The electronic apparatus includes: a camera; a processor configured to control the camera; and a memory configured to be electrically connected to the processor and to store a network model trained to determine a degree of matching between an input image frame and predetermined feature information, wherein the processor is configured to: identify a representative image frame based on a degree of matching obtained by applying image frames, selected from among a plurality of image frames, to the trained network model, while the plurality of image frames are captured through the camera, identify a best image frame based on a degree of matching obtained by applying image frames within a specific section including the identified representative image frame, to the trained network model, and provide the identified best image frame.

Electronic apparatus, controlling method of electronic apparatus, and computer readable medium

An electronic apparatus is provided. The electronic apparatus includes: a camera; a processor configured to control the camera; and a memory configured to be electrically connected to the processor and to store a network model trained to determine a degree of matching between an input image frame and predetermined feature information, wherein the memory stores at least one instruction, and wherein the processor is configured, by executing the at least one instruction, to: identify a representative image frame based on a degree of matching obtained by applying image frames, selected from among a plurality of image frames, to the trained network model, while the plurality of image frames are captured through the camera, identify a best image frame based on a degree of matching obtained by applying image frames within a specific section including the identified representative image frame, to the trained network model, from among the plurality of image frames, and provide the identified best image frame.

A method of manufacturing a semiconductor device includes forming a plurality of recess regions on an upper surface of a substrate, forming a first oxide layer in the recess regions, forming a polysilicon layer on the first oxide layer, forming a second oxide layer by oxidizing the polysilicon layer, and forming a gap-fill layer on the second oxide layer to fill the recess regions, wherein at least a portion of the polysilicon layer remains between the first oxide layer and the second oxide layer after forming the second oxide layer.

Semiconductor devices including device isolation structures and methods of manufacturing the same

Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.

Growing community of inventors

Yongin-si, South Korea

Dongjin Jung