Samsung Electronics Co., Ltd.

Dongil Lee

Younghun Seo

Sangyun Kim

Bokyeon Won

Hoseok Lee

Kangsub Jeong

A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

Memory core circuits having cell-on-periphery structures and memory devices including the same

A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

Volatile memory device and data sensing method thereof

Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.

Growing community of inventors

Hwaseong-si, South Korea

Dongil Lee