Samsung Electronics Co., Ltd.

Dongil Bae

Joohee Jung

Taeyoung Kim

Daewon Kim

Jinbum Kim

Jaehoon Shin

Beomjin Park

Kang-ill Seo

Kyungsoo Kim

Changwoo Oh

Changhee Kim

Sungman Whang

Li Ming

Sangpil Sim

A semiconductor integrated circuit device including a substrate with a first element region of a P type and a second element region of an N type, a channel active region that extends in the first element region or the second element region, the channel active region including a plurality of channels, a plurality of gate lines that extend in a second direction intersecting and include a gate metal layer, and a gate insulating film in contact with the gate metal layer, a plurality of first spacers on opposite side portions of respective ones of the gate lines, and a plurality of source/drain regions that are between ones of the plurality of gate lines. The channel active region includes a first channel directly on the substrate, and a second channel spaced apart from the first channel and extends into the gate metal layer.

Semiconductor integrated circuit device and manufacturing method thereof

A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

Semiconductor device including active region and gate structure

A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

Semiconductor device

Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.

Methods of fabricating devices including source/drain region with abrupt junction profile

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Seongnam-si, South Korea

Dongil Bae