Samsung Electronics Co., Ltd.

Sungkyunkwan University

Donghyuk Lim

Youngho Choi

June-Hee Lee

Kyeongjoon Ko

Byungwook Cho

Junghoon Chun

Wook Rae Kim

Dasom Park

Inhwan Song

Youngseob Suh

Kibaek Kwon

Byoungjoo Yoo

A receiver is provided. The receives includes: a signal detection circuit configured to receive differential signals having a variable data rate, and provide a detection signal based on the differential signals corresponding to a first data pattern of a first frequency, wherein the first data pattern of the first frequency indicates an exit from an electrical idle state; an analog-digital converter circuit configured to generate sample data by sampling the differential signals at a second frequency, and identify whether the sample data corresponds to a second data pattern which indicates normal data; and a control circuit configured to enable the analog-digital converter circuit based on the detection signal, and store the sample data. The first frequency is lower than the second frequency.

Receiver, interface circuit including the same, and method of operating receiver

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

Electronic device, operating method thereof, and electronic system

An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.

Apparatus and method for channel equalization based on error detection

A signal receiving circuit may include a receiving equalizer and a sequence estimator. The receiving equalizer may be configured to compensate an inter-symbol interference in a signal from an external to output an equalization data, based on a receiving signal from an outside. The sequence estimator may be configured to determine a termination symbol, based on the equalization data, to perform a decoding on the receiving signal, based on the determined termination symbol, and to output the decoded receiving signal as a sequence data.

Signal receiving circuit and operation method thereof

A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.

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Seoul, South Korea

Donghyuk Lim