Atomera Incorporated

Donghun Kang

A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate with adjacent gate stacks defining a respective trench therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and respective conductive contact liners in the trenches.

Method for making nanostructure transistors with source/drain trench contact liners

A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate defining respective trenches therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, forming respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures and flush with adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Method for making nanostructure transistors with flush source/drain dopant blocking structures including a superlattice

A method for making semiconductor device may include forming spaced apart gate stacks on a substrate defining respective trenches therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, forming respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

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San Jose, CA, United States of America

Donghun Kang