Samsung Electronics Co., Ltd.

Donghun Heo

Cheolhwan Lim

Kwangho Kim

Jonghyuk Cho

Sangjin Lim

Masato Suzuki

Norio Okada

Yongjin Lee

Eunhye Kim

Junhyeok Yang

Tae-Hwang Kong

Haejung Choi

Himchan Park

Daesun Rhee

A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

Laser detecting circuit and semiconductor apparatus including the same

A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

Semiconductor devices comprising failure detectors for detecting failure of bipolar junction transistors and methods for detecting failure of the bipolar junction transistors

A low voltage attack detector includes: a low voltage detector configured to output a low voltage detection flag signal having a high level when a first power supply voltage reaches a first voltage level using a bandgap reference (BGR) circuit including a PMOS transistor and a first bipolar junction transistor (BJT) connected in series between the first power supply voltage and a second power supply voltage; a BGR operation region detector configured to output a malfunction detection flag signal having a high level when the first power supply voltage reaches a second voltage level lower than the first voltage level; and a logic gate configured to output a final low voltage detection flag signal having a high level when at least one of the low voltage detection flag signal and the malfunction detection flag signal has a high level.

Low voltage attack detector, secure element and electronic system including the same

A semiconductor device includes a sensing circuit including a first semiconductor element configured to generate a first current in response to externally incident light, a compensation circuit including a semiconductor element configured to generate a second current depending on an ambient temperature and to remove the second current from the first current to generate a third current, a detection circuit configured to convert the third current into a photovoltage and to compare the photovoltage with a predetermined reference voltage to determine whether an external attack has occurred, and a defense circuit configured to control the semiconductor device to perform a predetermined defense operation, based on a result of the determination.

Defense circuit of semiconductor device and semiconductor device including the same

A glitch detector includes a sensing circuit, a glitch-to-pulse generator and a comparing circuit. The sensing circuit generates a glitch voltage and at least one reference voltage based on a first power supply voltage. The glitch-to-pulse generator receives the first power supply voltage or the glitch voltage, and generates at least one pulse voltage including a pulse when the glitch occurs on the first power supply voltage. The comparing circuit generates at least one detection voltage by comparing the glitch voltage with the at least one reference voltage based on the pulse included in the at least one pulse voltage. The at least one detection voltage is activated when the glitch occurs on the first power supply voltage.

Glitch detector, security device including the same and electronic system including the same

An electronic device includes a battery, a charging integrated circuit (IC) configured to control a charging state of the battery, a connector pin for receiving power from an external device, the connector pin including a first connector pin for receiving a high potential voltage from the external device and a second connector pin for receiving a low potential voltage from the external device, a touch sensor, and a controller. The controller receives power from the external device through the connector pin based on the detection of the external device being connected to the connector pin, charges the battery using a high potential voltage, detects a user input through the touch sensor while the battery is charged, and stops the charging of the battery and outputs a current corresponding to state information of the electronic device through the first connector pin based on the detection of the given user input.

Electronic device and method for communicating with external device through power source line

A regulator includes a first resistor and a second resistor that are connected between a ground node and an output node, an amplifier that outputs an amplification voltage by comparing a reference voltage to a feedback voltage between the first resistor and the second resistor, and amplifying a difference between the reference voltage and the feedback voltage, an analog-to-digital converter that converts the amplification voltage to a digital code, and a plurality of transistors that are connected between a power node supplied with a power supply voltage and the output node and which adjusts a current being supplied to the output node in response to the digital code.

Regulator and method of operating regulator

An electronic device according to various embodiments of the present disclosure may include a communication interface and a processor, wherein the processor may be configured to receive first battery level information of a first earpiece and second battery level information of a second earpiece, via the communication interface, to identify a charging method corresponding to the first battery level and the second battery level, among a plurality of charging methods for charging at least one of the first earpiece or the second earpiece, and to control to supply charging power to at least one of the first earpiece or the second earpiece, via a cable which connects the electronic device with at least one of the first earpiece or the second earpiece, using the charging method.

Growing community of inventors

Hwaseong-si, South Korea

Donghun Heo