Samsung Electronics Co., Ltd.

Donghoon Kwon

Chungki Min

Yeoseon Choi

Boun Yoon

Junsuk Kim

Ilyoung Yoon

Hyojung Kim

Chang-Sun Hwang

Jongheun Lim

Chanwook Seo

A slurry arm is provided. The slurry arm includes: an arm body; a slurry line that extends through the arm body; an oxygen removal chamber provided in the arm body and configured to receive slurry from the slurry line; a purge gas supplier configured to supply a purge gas to the slurry in the oxygen removal chamber; and a main valve configured to selectively discharge gas from the oxygen removal chamber.

Slurry arm and chemical mechanical polishing apparatus including the same

A semiconductor substrate grinding apparatus including a chuck table configured to mount and fix a semiconductor substrate, so that a back side of the semiconductor substrate faces upwardly and rotates in one direction; a grinding wheel on the chuck table configured to grind the back side of the semiconductor substrate; a cleaning liquid supplier on the chuck table, spaced apart from the grinding wheel, and configured to supply a cleaning liquid to the back side of the semiconductor substrate for cleaning by-products generated by grinding the semiconductor substrate; a slurry supplier on the chuck table, adjacent to the cleaning liquid supplier, and configured to supply a slurry to the back side of the semiconductor substrate; and a polishing wheel on the chuck table, spaced apart from the slurry supplier, and configured to perform chemical mechanical polishing on the back side of the semiconductor substrate using the slurry.

Semiconductor substrate grinding apparatus for simultaneous grinding and polishing of backside of wafer

A sample holder includes a head, a first holding plate extending in a first direction from one surface of the head and including at least one first sample hole configured to accommodate at least one first sample and a first main surface configured such that the at least one first sample accommodated in the at least one first sample hole is exposed at the first main surface, and a second holding plate extending in the first direction from the one surface of the head and including at least one second sample hole configured to accommodate at least one second sample and a second main surface configured such that the at least one second sample accommodated in the at least one second sample hole is exposed at the second main surface, wherein a direction perpendicular to the first main surface of the first holding plate differs from a direction perpendicular to the second main surface of the second holding plate.

Sample holder of transmission electron microscope and semiconductor device inspection method using the sample holder

A sample holder for a transmission electron microscope may include: a column part that extends in a first direction; a stage configured to receive a sample, the stage disposed at a first end portion of the column part; a motor part disposed at a second end portion of the column part; and a thermoelectric cooling device disposed inside the column part.

Sample holder for transmission electron microscope, sample analysis system including the same, and method for analyzing sample using the same

A semiconductor device includes a first substrate; circuit elements on the first substrate; lower interconnection lines electrically connected to the circuit elements; a second substrate on the lower interconnection lines; gate electrodes spaced apart from each other and stacked on the second substrate in a first direction that is perpendicular to an upper surface of the second substrate; channel structures penetrating through the gate electrodes, extending in the first direction, and respectively including a channel layer; through-vias extending in the first direction and electrically connecting at least one of the gate electrodes or the channel structures to the circuit elements; an insulating region surrounding side surfaces of through-vias; and a via pad between the through-vias and at least one of the lower interconnection lines in the first direction and spaced apart from the second substrate in a second direction, parallel to an upper surface of the second substrate.

Semiconductor devices and data storage systems including the same

A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.

Semiconductor device and electronic system including the same

A memory device includes a cell stacked structure on a substrate, the cell stacked structure including insulation layers and gate patterns alternately stacked, a channel structure passing through the cell stacked structure, the channel structure extending in a vertical direction, a dummy structure on the substrate, the dummy structure being spaced apart from the cell stacked structure, and the dummy structure including insulation layers and metal patterns alternately stacked, a first through via contact passing through the dummy structure, the first through via contact extending in the vertical direction, and a first capping insulation pattern between a sidewall of the first through via contact and each of the metal patterns in the dummy structure, the first capping insulation pattern insulating the first through via contact from each of the metal patterns.

Memory device

A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure.

Growing community of inventors

Hwaseong-si, South Korea

Donghoon Kwon