International Business Machines Corporation

Dongho Lee

Antonio R Pelella

Gerard M Salem

Vinod Ramadurai

Robert Maurice Houle

Stephen Frank Geissler

Brian James Yavoich

Mathew I Ringler

Miles G Canada

Timothy J Vonreyn

Zhiying Chen

Genadi Tverskoy

Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.

Local bit select with improved fast read before write suppression

A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.

Method and circuit for dynamic read margin control of a memory array

Growing community of inventors

Poughkeepsie, NY, United States of America

Dongho Lee