Samsung Electronics Co., Ltd.

Donggun An

Jaehyeok Baek

Sung-Yong Cho

Daehyun Kwon

SungYong Cho

Hyejung Kwon

MoonChul Choi

Daewoong Lee

Moon-Chul Choi

A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.

ZQ calibration circuit, operation method of the ZQ calibration circuit, and semiconductor memory device

In a transmitter circuit, an impedance calibration circuit is configured to generate an impedance code for impedance matching, an encoder is configured to receive the impedance code and to generate a delay compensation signal based on the impedance code. A delay circuit is configured to output delay data that are delayed from input data by a delay value determined based on the delay compensation signal. A feed-forward equalizer is configured to receive the input data and the delay data, and to equalize the input data based on a main coefficient used for the input data and an equalization coefficient used for the delay data to generate transmission data.

Transmitter circuit and operation method thereof

A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.

Calibration circuit and semiconductor device including the same

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Suwon-si, South Korea

Donggun An