Intel Corporation

Dongdong Chen

Martin Langhammer

Jason R Bergendahl

Kevin Hurd

Jung Ko

An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Integrated circuits with machine learning extensions

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

FPGA specialist processing block for machine learning

An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

An integrated circuit includes first and second circuit blocks. The first circuit block includes a first storage circuit. A first data path passes through the first storage circuit and a first multiplexer circuit to a first input of a first logic circuit. The first multiplexer circuit is coupled to the first storage circuit. A second storage circuit is coupled between the first storage circuit and the first multiplexer circuit. A second data path passes through the second circuit block to a second input of the first logic circuit. The first multiplexer circuit is configurable to bypass or to couple the second storage circuit in the first data path based on an indication of whether a redundant third circuit block is coupled between the first and second circuit blocks in at least one of the first data path or the second data path.

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Union City, CA, United States of America

Dongdong Chen