International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Dongbing Shao

Zheng Xu

Markus Brink

Lawrence Alfred Clevenger

Robert C Wong

Jing Sha

Fee Li Lie

Yongan Xu

Yang Liu

Geng Han

Firat Solgun

Dureseti Chidambarrao

Zhenxing Bi

Qianwen Chen

Jared Barney Hertzberg

Kangguo Cheng

Chen Zhang

Rasit Onur Topaloglu

Kafai Lai

Jason D Hibbeler

Kehan Tian

Chieh-Yu Lin

Tenko Yamashita

Ruqiang Bao

Jerry M Chow

Salvatore Bernardo Olivadese

Shyng-Tsong Chen

Martin O Sandberg

Shayak Banerjee

Eric Peter Lewandowski

Todd Christopher Bailey

Martin Burkhardt

Steven Zebertavage

Daniel S Fischer

Michael A Guillorn

Lars W Liebmann

Kirk David Peterson

Jae-Woong Nah

Kai D Feng

Alan Edward Rosenbluth

Sean David Burns

James A Culp

Vivekananda P Adiga

Nicholas Torleiv Bronn

Hao Tang

Derren Neylon Dunn

George Andrew Keefe

Lei L Zhuang

John Blair

Srikanth Srinivasan

Chieh-yu Lin

Jinning Liu

Yuping Cui

Yufei Wu

Thomas George McConkey

First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

Devices and/or computer-implemented methods to facilitate a multipole filter on a quantum device with multiplexing capability and signal separation to mitigate crosstalk are provided. According to an embodiment, a device can comprise an interposer substrate comprising a readout resonator. The device can further comprise a qubit chip substrate comprising a qubit coupled to the readout resonator and to a multipole filter.

Multipole filter on a quantum device with multiplexing and signal separation

Systems and techniques that facilitate uniform qubit chip gaps via injection-molded solder pillars are provided. In various embodiments, a device can comprise one or more injection-molded solder interconnects. In various aspects, the one or more injection-molded solder interconnects can couple at least one qubit chip to an interposer chip. In various embodiments, the device can further comprise one or more injection-molded solder pillars. In various instances, the one or more injection-molded solder pillars can be between the at least one quit chip and the interposer chip. In various cases, the one or more injection-molded solder pillars can be in parallel with the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can facilitate and/or maintain a uniform gap between the at least one qubit chip and the interposer chip. In various embodiments, a melting point of the one or more injection-molded solder pillars can be higher than a melting point of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be superconductors. In various embodiments, a yield strength of the one or more injection-molded solder pillars can be between 3,000 pounds per square inch and 15,000 pounds per square inch, which can be higher than a yield strength of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be binary tin alloys, tertiary tin alloys, and/or quaternary tin alloys.

Uniform chip gaps via injection-molded solder pillars

A method of frequency allocation in a quantum device having a plurality of qubits includes determining a plurality of frequency groups based on a configuration of the plurality of qubits; determining, for each of the plurality of qubits, a qubit frequency; assigning a frequency group from the plurality of frequency groups to each of the plurality of qubits based on each respective qubit frequency; determining for at least one qubit of the plurality of qubits whether a frequency collision exists between the at least one qubit and neighboring qubits in the plurality of qubits based on the qubit frequency of the at least one qubit and at least one qubit frequency of the neighboring qubits; and adjusting the frequency of the at least one qubit based on the determination whether a frequency collision exists between the at least one qubit and said neighboring qubits in the plurality of qubits. A non-transitory computer-readable medium for frequency allocation in a quantum device includes instructions to perform the method.

Color-map method to eliminate qubit frequency crowding in a quantum computing chip

A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.

Circuit wiring techniques for stacked transistor structures

A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Self-aligned double patterning with spacer-merge region

Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Addressing layout retargeting shortfalls

According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.

Highway jumper to enable long range connectivity for superconducting quantum computer chip

A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission.

Coupled-line bus to suppress classical crosstalk for superconducting qubits

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Bump connection placement in quantum devices in a flip chip configuration

Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.

Hybrid readout package for quantum multichip bonding

Growing community of inventors

Wappingers Falls, NY, United States of America

Dongbing Shao