No. 24 Research Institute of China Electronics Technology Group Corporation

Chongqing Gigachip Technology Co. Ltd.

China Electronic Technology Corporation, 24th Research Institute

No. 24 Research Institute of China Electronic Technology Corporation

China Electronics Technology Group Corporation No. 24 Research Institute

Congqing Gigachip Technology Co., Ltd.

Dongbing Fu

Guangbing Chen

Jian'an Wang

Ruzhang Li

Yuxin Wang

Ting Li

Gangyi Hu

Yong Zhang

Daiguo Xu

Yabo Ni

Liang Li

Zhengping Zhang

Xiaofeng Shen

Jianan Wang

Zhengbo Huang

Hequan Jiang

Tao Liu

Mingyuan Xu

Xingfa Huang

Rongbin Hu

Yan Wang

Can Zhu

Xi Chen

Lu Liu

Zicheng Xu

Xueliang Xu

Zhou Yu

Xu Wang

Minming Deng

Jie Pu

Shiliu Xu

Youhua Wang

Yonglu Wang

Jun Luo

Shengdong Hu

Huaiqiang Yu

Chao Chen

Jun Liu

Lei Zhang

Hanfu Shi

Jun Yuan

Yuhan Gao

Zhihua Feng

Rongke Ye

Ruitao Zhang

Junan Zhang

Ziqiang Yi

Gang Zhou

Dong Tang

Ning Tang

Xiaoquan Yu

Hongrui Yang

Zhimei Yang

Min Gong

Jiahao Peng

Shuiqin Yao

Xianjie Wan

A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher. An actual weight of each quantization unit at each conversion stage, an actual inter-stage gain of each conversion stage and an actual weight of jitter are extracted, impact of a jitter weight is eliminated during outputting, and a signal-to-noise ratio of analog-to-digital conversion is increased.

Method for correcting analog-to-digital converter

A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.

Method for calibrating analog-to-digital converter

A differential-follower control circuit has been provided, comprising: a follower; an output-voltage following module, which controls a voltage at a control terminal of the follower to vary with an output voltage; a substrate-voltage following module, which controls a substrate voltage of an output transistor of the follower to vary with an input voltage; an output terminal of the follower is connected to a first terminal of the output-voltage following module; a second terminal of the output-voltage following module is connected to the control terminal of the follower; a first terminal of the substrate-voltage following module is connected to an input terminal of the follower and a second terminal of the substrate-voltage following module is connected to a substrate of the output transistor; the invention effectively improves the overall linearity of the follower.

Differential-follower control circuit

Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.

Circuits, chips, systems and methods for eliminating random perturbation

The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter. A polysilicon resistor includes a first silicon substrate; a first silicon oxide layer disposed on the first silicon substrate; a second silicon substrate disposed on the first silicon oxide layer, wherein an insulating isolation structure extends through the second silicon substrate and divides the second silicon substrate into a plurality of substrate isolation areas separated from each other; a second silicon oxide layer disposed on the second silicon substrate; and a polysilicon resistor layer disposed on the second silicon oxide layer, wherein the polysilicon resistor layer includes a plurality of polysilicon resistor blocks separated from each other, the plurality of polysilicon resistor blocks is arranged in one-to-one correspondence with the plurality of substrate isolation areas, and the plurality of polysilicon resistor blocks are connected in series.

Polysilicon resistors, methods for manufacturing the same, and successive approximation register analog-to-digital converter

The comparator includes an input unit, a load unit, a control switch, and an adjustment unit. The input ends of the input unit are connected to a first input signal and a second input signal. The load unit is connected to the input unit, and the gain of the comparator is adjusted by changing the gate voltages of the pair of gain adjustment transistors of the load unit. The adjustment unit is connected to the input unit, and the gate voltages of the pair of gain adjustment transistors are adjusted according to the enable state of the control switch. The present disclosure also provides an analog-to-digital converter.

Comparator and analog-to-digital converter

A digital temperature sensor circuit is disclosed. The digital temperature sensor circuit includes a proportional to the absolute temperature (PTAT) current source, generating a PTAT current proportional to absolute temperature; a sigma-delta modulation module, including an integrator, an analog-to-digital conversion unit, and a feedback digital-to-analog conversion unit; the integrator converts the PTAT current into temperature voltage; the analog-to-digital conversion unit compares the temperature voltage with a band gap reference voltage to generate a digital modulation signal with a duty ratio proportional to the temperature; the feedback digital-to-analog conversion unit adjusts the voltage input by the analog-to-digital conversion unit and controls the charging and discharging speed of the integrator; a digital filter, quantizing the digital modulation signal into a digital signal, and outputting the digital signal.

Digital temperature sensor circuit

A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Follow-hold switch circuit

An interface circuit and an electronic apparatus, including: a programmable current array (), generating a first current and a second current transmitted to a common mode and differential mode generation circuit () according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit () according to the input code; the common mode and differential mode generation circuit (), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Interface circuit and electronic apparatus

The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

High-speed digital logic circuit for SAR_ADC and sampling adjustment method

A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve

The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.

Substrate-enhanced comparator and electronic device

A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Highly linear time amplifier with power supply rejection

A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Pipelined analog-to-digital converter and output calibration method thereof

SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

SAR ADC and sampling method based on single-channel time-interleaved-sampling

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Chongqing, China

Dongbing Fu