Samsung Electronics Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Dong-young Chang

Seung-hoon Lee

Jin-kuk Lee

You-jin Cha

Geun-soon Kang

Yong-In Park

Hee-Cheol Choi

Jae-yup Lee

Geun-Soon Kang

You-Mi Lee

Seung Woo Park

A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal. According to the gain controller using switched capacitors, it is possible to automatically control the gain of an input signal at high speed and to reduce power consumption since the time required for settling the gain of the input signal to a desired value is short.

Gain controller using switched capacitors

An analog/digital (A/D) converting circuit is provided that stabilizes system operation, reduces power consumption in an analog circuit region and uses a selected metal-to-metal capacitor, which has a small parasitic capacitance value. The A/D converting circuit includes a first sample/hold amplifier for sampling/holding an analog input signal, a switch for selecting one of a signal outputted from the first sample/hold amplifier and a feedback signal and an A/D sub-converter for converting an analog signal outputted from the switch to a digital signal. A multiplying D/A converting block converts an output signal from the A/D sub-converter to an analog signal and amplifies a difference value obtained between the analog signal and the analog signal outputted from the switch. A second sample/hold amplifier samples/holds a signal outputted from the multiplying D/A converting block and outputs the feedback signal to the switch. A digital correcting unit outputs an N bit digital signal by superimposing output signals from the A/D sub-converter by 1 bit and a timing controller generates a control signal and a timing clock signal for the operation of each unit.

Analog/digital converting circuit

Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

CMOS operational amplifiers having reduced power consumption

Growing community of inventors

Seoul, South Korea

Dong-young Chang