Skhynix Inc.

Dong Yoon Ka

Gi Moon Hong

Jin Yong Min

A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.

Semiconductor device related to operation of internal circuits

A semiconductor device may include a first column decoder arranged at a first side of a bank, wherein the first column decoder is enabled by a first column decoder select signal. The semiconductor device may include a second column decoder arranged at a second side of the bank, wherein the second column decoder is enabled by a second column decoder select signal; and wherein the bank is arranged between the first column decoder and the second column decoder. The semiconductor device may further include a column decoder selection circuit suitable for activating any one of the first and second column decoder select signals based on a row address.

Semiconductor device

The semiconductor device may include an address conversion circuit configured for generating a variable address. The semiconductor device may include a column decoder configured for generating a first output select signal or a second output select signal from a column address based on the variable address.

Apparatus and method for non-volatile memory address decoding

A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write precharge signal in response to a write burst end signal activated after a write burst operation and a read precharge signal in response to a read burst end signal activated after a read burst operation. The bank address controller generates a write address and a read address designating an address for the precharge operation in response to a write bank address and a read bank address. The precharge signal generator generates a precharge signal for performing the precharge operation in a bank selected in response to the write address when the write precharge signal is activated, or generates a precharge signal for performing the precharge operation in a bank selected in response to the read address when the read precharge signal is activated.

Precharge control device and semiconductor device including the same

A semiconductor device may be provided. The semiconductor device may include a target address storage circuit and a first row address generation circuit. The target address storage circuit may be configured to count the number of times that blocks are selected by a plurality of logic level combinations of an address based on an active pulse. The target address storage circuit may be configured to store and output the address of a target block, which is selected at least a predetermined number of times, among the blocks as a target address. The first row address generation circuit may be configured to generate a first row address, which is counted, from the target address based on a first internal command.

Semiconductor device relating to generate target address to execute a refresh operation

A semiconductor device includes a skew sensing block configured to generate a first output signal according to a driving force for driving a first internal node and generate a second output signal according to a driving force for driving a second internal node, in response to an input signal; and a skew control signal generation block configured to generate skew control signals for controlling a skew of an internal circuit, by the first and second output signals.

A semiconductor memory apparatus includes an internal data generation block configured to generate test data in response to test signals, and output ones of normal data inputted from data input/output pads and the test data as internal data according to a test flag signal; a data storage region configured to receive and store the internal data, and output stored data as cell storage data; a latch block configured to receive and store the cell storage data in response to a data output enable signal, and output stored data as latch data; and a data comparison block configured to compare the test data and the latch data, and generate a test result signal.

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Icheon-si, South Korea

Dong Yoon Ka