Taiwan Semiconductor Manufacturing Comp. Ltd.

Dong-Yo Jheng

Ru-Gun Liu

Ken-Hsien Hsieh

Shih-Ming Chang

Shuo-Yen Chou

Chih-Jie Lee

Chih-Ming Lai

Wen-Li Cheng

A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Optical proximity correction and photomasks

A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.

A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.

Hybrid double patterning method for semiconductor manufacture

Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

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Hsinchu, Taiwan

Dong-Yo Jheng