Samsung Electronics Co., Ltd.

Dong-yean Oh

Woon-Kyung Lee

Chang-Sub Lee

Seung-Chul Lee

Jai-Hyuk Song

Chang-Hyun Lee

Hyun-Jae Kim

Jeong-Hyuk Choi

Jai Hyuk Song

An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

NAND flash memory device and method of making same

Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers may be directly over a dummy well.

Semiconductor device comprising a dummy well

An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL&#x3c;i&#x3e;, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Chfrom a second local channel Ch. As the location i of the selected wordline WL&#x3c;i&#x3e; increases close to the SST, the second channel potential Vchtends to increase excessively, causing errors. The excessive increase of Vchis prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL&#x3c;i+1 through WL&#x3c;n&#x2192;), only if the selected wordline WL&#x3c;i&#x3e; location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.

NAND flash memory device and method of operating same to reduce a difference between channel potentials therein

A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

Methods of fabricating non-volatile memory devices including double diffused junction regions

A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.

Nonvolatile semiconductor device and memory system including the same

Non-volatile memory devices including double diffused junction regions

A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

Growing community of inventors

Seoul, South Korea

Dong-yean Oh