Samsung Electronics Co., Ltd.

Dong-Yang Lee

Sun-Young Lim

Ju-yun Jung

Kyeong-Han Lee

Bu-Il Jung

Min-Yeab Choo

Jong-Hyun Choi

Young-Jin Cho

Oh-seong Kwon

Do-Geun Kim

Seok-Cheon Kwon

Hyuk Soo Han

Doo-Hee Hwang

Mi-Kyoung Park

Jung-Bae Lee

Jung-bae Lee

Kwang-Hyun Kim

Ki-Seok Oh

Sung-Ho Cho

Seok-cheon Kwon

Jae-Hyeong Lee

Sang-Kyu Kang

Do-Kyun Kim

Jae-Yeon Choi

Keun-soo Jo

Joon-Kun Kim

Hee-Joo Choi

Jung-Bae 523-302 Samsung 5-Cha Apt Lee

An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

Memory system and electronic device

A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

Memory system capable of re-mapping address

A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.

Stacked memory chip having reduced input-output load, memory module and memory system including the same

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Flash memory device for outputing data in synch with a first signal in an SDR mode and a DDR mode and a flash memory system including the same

A method of operating a memory device includes writing cell data having one of at least three states to a memory cell; amplifying a voltage level of a bit line connected to the memory cell; determining that the cell data is in a first state when the voltage level of the bit line sensed at a sensing point is equal to or greater than a first reference voltage; determining that the cell data is in a second state when the voltage level of the bit line sensed at the sensing point is equal to or less than a second reference voltage which has a lower voltage level than the first reference voltage; and determining that the cell data is in a third state when the cell data is not in the first or second states.

Memory device and a method of operating the same

A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Semiconductor memory devices, memory systems including refresh control circuit and method of performing weak refresh operation on the weak pages thereof

A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.

Memory device and computing system including the same

A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

Method of repairing a memory device and method of booting a system including the memory device

Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same

Flash memory device and flash memory system including the same

A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.

Multi-chip package semiconductor memory device providing active termination control

The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.

Memory system, a memory device, a memory controller and method thereof

Semiconductor memory devices are provided. The semiconductor memory device includes a command decoder, a code converter and a code outputting unit. The command decoder is configured to receive a plurality of command signals from an external source, decode the plurality of command signals and generate a mode register reading signal responsive to the decoded plurality of command signals. The code converter is configured to receive mode setting codes generated based on the decoded plurality of command signals and convert the mode setting codes to serial mode setting codes. The code outputting unit is configured to receive the serial mode setting codes and output the serial mode setting codes to the external source responsive to the mode register reading signal. Systems including the semiconductor memory devices are also provided.

Semiconductor memory devices including mode registers and systems including the same

Provided is a memory system in which a pair of differential signals transmitted via a pair of transmission lines are prevented from being terminated at the same voltage during a standby mode, thereby preventing a receiver from entering an unstable state. The memory system includes a pair of transmission lines, a transmitter that outputs a pair of differential signals to the pair of transmission lines, and a receiver that receives the pair of differential signals via the pair of transmission lines. A first termination voltage is applied to one of the pair of transmission lines, and a second termination voltage is applied to the other transmission line. The first termination voltage is determined to be different from the second termination voltage.

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Yongin-si, South Korea

Dong-Yang Lee