Samsung Electronics Co., Ltd.

Dong-Wook Seo

Jae-Seung Choi

Sang-Yeop Baeck

Tae-Hyung Kim

Hyunsu Choi

Hoon Bae Kim

Taejoong Song

Jisu Yu

Inhak Lee

Daeyoung Moon

Jung-Myung Kang

Sun-Yung Jang

Chan-Ho Lee

Il-Yong Jong

Hee-Su Kim

Jong-Hoon Jung

Tae-hyung Kim

Hyun-Su Choi

Dae-young Moon

In-Gyu Park

In-Hak Lee

Gi-Bong Jeong

Siddharth Gupta

Da-Som Lee

Moon-Kyung Kim

Gyuhong Kim

Jaeseung Choi

Dae Young Moon

Myeong-Jin Oh

Ho Young Tang

Se-Yeong Lee

Seong-Hun Moon

Provided are a three-dimensional (3D) semiconductor integrated circuit and a static random access memory (SRAM) device. The three-dimensional (3D) semiconductor integrated circuit includes: a first die including a power supply circuit a second die including an SRAM with a through-silicon-via (TSV) bundle region; a third die including a processor; and TSVs, each of which is provided on the TSV bundle region and extends from the TSV bundle region to the third die. The SRAM device includes: a bank array with banks, each of which includes sub-bit-cell arrays and a local peripheral circuit region arranged in a cross (+) shape between the sub-bit-cell arrays; and a global peripheral circuit region including a tail peripheral circuit region extending in a first direction and a head peripheral circuit region extending in a second direction, the tail peripheral circuit region and the head peripheral circuit region being arranged in a 'T' shape.

SRAM device and 3D semiconductor integrated circuit thereof

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Semiconductor device for selectively performing isolation function and layout displacement method thereof

An electronic device is provided. The electronic device includes a housing, a touchscreen display, a wireless communication circuit, a processor electrically connected to the touchscreen display and the wireless communication circuit, and a memory electrically connected to the processor, wherein the memory is configured to store an application program comprising a user interface, and store an instruction that, when executed, enables the processor to store a permission for accessing, by an application program stored in the memory, at least one among hardware components or software components of the electronic device, activate the application program, allow the application program to access the at least one among hardware components or software components based on the stored permission and display a user interface (UI) of the application program on the touchscreen display, hide a part of the user interface while the application program is executed in a background state, and monitor whether the application program uses the at least one among hardware components or software components while the application program is executed in the background state.

Method and electronic device for controlling permission of application program

Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Voltage control circuit including assist circuit and memory device including the same

Layout of semiconductor device for selectively operating as insulating circuit or driving circuit

A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Volatile memory device and system-on-chip including the same

A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.

Scan chain circuit and integrated circuit including the same

A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

System on chip including dual power rail and voltage supply method thereof

A method and mobile device for decoding a paging message transmitted as multiple bursts in a wireless communication system are provided. In the method, only the first burst among four bursts of a transmitted paging message is received and equalized. The equalized first burst is compared (e.g., by computing correlation) with a reference paging message. The first comparison result value obtained from the first comparison is compared with a threshold value. If the first comparison result value is greater than the threshold value, second through fourth bursts of the paging message are not received, and a previous decoded paging message is output and a sleep state is entered. If the comparison result value is not greater than the threshold value, the second through fourth bursts are received and decoded, the decoded paging message is encoded, and a first burst of the encoded paging message is stored as the reference paging message.

Method and apparatus for decoding paging message in wireless communication system

A method of decoding a control channel in a wireless communication system is provided. In the method, a terminal calculates the number of sub-bursts to be used during a next decoding and positions of the sub-bursts, based on a signal-to-noise ratio of at least one of a first burst or a second burst. Then, the terminal compares the calculated number of sub-bursts with a reference value. When the calculated number of sub-bursts is greater than the reference value, the terminal does not receive more bursts or sub-bursts and instead enters into a sleep state. When the calculated number of sub-bursts is smaller than or equal to the reference value, the terminal receives and decodes only sub-bursts at the calculated positions.

Method and apparatus for decoding a control channel in a wireless communication system

An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first 'overlapping' operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.

Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations

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Hwaseong-si, South Korea

Dong-Wook Seo