Skhynix Inc.

Hynix Semiconductor Inc.

Dong-Wook Jang

Jin-Woo Choi

Yong-Mi Kim

A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.

Decoding circuit and method of decoding signal

A data transmission circuit includes a first data selection unit suitable for alternately outputting data of first and second input lines as first driving data in synchronization with a clock; a data delay unit suitable for generating first and second delay data by delaying the data of the first and second input lines in synchronization with the clock; a second data selection unit suitable for: alternately outputting the data of the first and second input lines as second driving data in synchronization with the clock during a first mode, and alternately outputting inverted first and second delay data, which are inverted from the first and second delay data, as the second driving data in synchronization with the clock during a second mode; a first driving unit suitable for driving an output line in response to the first driving data; and a second driving unit suitable for driving the output line in response to the second driving data.

Data transmission circuit

A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y.

Growing community of inventors

Gyeonggi-do, South Korea

Dong-Wook Jang