Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Dong-woo Lee

Jung-yong Choi

Seong-hun Jeong

Houng-sog Min

Shin-wook Kang

Hee-Chan Choi

Jong-Hyun Choi

Young-Jin Cho

Seung-Bum Kim

Jin-ha Kim

Sung-Un Park

Han-gu Sohn

Yong-suk Choi

Jin-hyoung Kwon

Yong-Won Shin

Ji-won Jeong

Moo-Youn Park

Jun-Won Kim

Hyang-suk Park

Oh-Sung Byun

Provided are a scan data processing method and apparatus. The method includes: performing a wireless communication connection with a predetermined user device during a scan mode; detecting user profile information corresponding to a user address of the predetermined user device; and controlling scan data based on the user profile information.

Method and apparatus for processing scan data

A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a memory control unit. The memory control unit is commonly connected to the first and second memory devices via a command/address bus and a portion of a data bus, and is connected to the second memory device via another portion of the data bus.

System and device having alternative bit organization

Provided are a method and apparatus capable of reducing a metadata processing time associated with address mapping performed to input/output burst data at a high speed in a virtual file system of a storage unit having a plurality of non-volatile data storage media. The method includes: determining a block group including a block included in each of a plurality of the non-volatile data storage media; determining an access unit including each page included in the determined block group; and mapping an address of input/output data to the determined block group and the access unit. Therefore, it is possible to significantly reduce an address mapping processing time in the virtual file system that may function as a bottleneck in high-speed input/output in a large-capacity storage unit.

Method and apparatus for performing address mapping in virtual file system of storage unit having a plurality of non-volatile data storage media

An organic light-emitting diode (OLED) display apparatus, including a control unit to receive an image signal and to generate a frame-based image data signal and a frame identification signal based at least in part on the received image signal, the frame identification signal being synchronized with the frame-based image data signal, a driving voltage supply unit to generate a first voltage for a switching unit and a second voltage for a display unit, and a switching unit to receive the first voltage and the frame identification signal and to supply the first voltage for the display unit based at least in part on the frame identification signal.

Organic light-emitting diode (OLED) display apparatus and method of driving the same

An apparatus and method for canceling a Direct Current (DC) offset in a Broadband Wireless Access (BWA) communication system are provided. The method includes canceling a DC offset by performing self-calibration in a modulator/demodulator (modem), attempting initial synchronization acquisition in the modem, and if the initial synchronization acquisition succeeds, canceling a DC offset by performing DC offset trace and cancellation.

Apparatus and method for canceling direct current (DC) offset in broadband wireless access communication system

A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.

Multi-path accessible semiconductor memory device with prevention of pre-charge skip

A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is commonly connected to the first and second memory devices via a command/address bus, and is connected to the first memory device via a data bus separate from the command/address bus and having an upper half and a lower half. However, the CPU is connected to the second memory device via only the upper half of the data bus.

Disclosed is an apparatus and a method for improving the receive (Rx) sensitivity of a portable Radio Frequency IDentification (RFID). The portable RFID reader/writer is equipped with a variable phase shifter which is connected between an antenna and a directional coupler and then changes an impedance in the direction of the antenna in response to controlling a phase shift, a level of a reflection signal if a transmit (Tx) signal of the portable RFID reader/writer reflected by the antenna flows into an Rx path is measured, and then the phase shift of the variable phase shifter is controlled in such a manner as to minimize the measured level of the reflection signal. Therefore, calibration is implemented so that an antenna impedance changing in response to a position in which contact is made by a user's hand may have an adaptively optimal antenna reflection coefficient, thereby improving the Rx sensitivity.

Apparatus and method for improving receiving sensitivity of portable radio frequency identification

A mobile terminal including an LED camera flash includes a lens, which is for photographing an object, an image sensing unit, which generates a sensor result value by executing automatic exposure and automatic white balance, a flash module, which includes a flash driving unit that controls the LED camera flash, an actuator, which moves the lens and records a distance traveled by the lens, and a camera control module, which sets an exposure gain value by using the sensor result value, extracts a distance current value and a distance gain value by using position information of the lens that is determined by using the distance traveled by the lens, and controls the flash driving unit so as to adjust a brightness of the LED camera flash according to a gain correction value, which is set by using the exposure gain value, the distance current value and the distance gain value.

Mobile terminal having camera flash and method for controlling camera flash

Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

Memory device input buffer, related memory device, controller and system

Provided are a flash memory system and a programming method performed in the flash memory system. The flash memory system includes a buffer unit including a plurality of buffers, and temporarily storing data transmitted by a host; a plurality of channel units each including at least one flash memory chip that includes a plurality of memory cell arrays; and a control unit which controls the data stored in the buffer unit to be sequentially transmitted to the channel units and the transmitted data to be recorded to the memory cell arrays of the flash memory chips in the channel units.

Flash memory system and programming method performed therein

A semiconductor memory device includes a mode register, an additional function executer, and an additional function controller. The mode register activates an additional function control signal when a mode register set code indicates that an additional function is to be executed concurrently with a refresh operation. The additional function controller controls the additional function executer to carry out the additional function concurrently with the refresh operation when the additional function control signal is activated.

Controlling execution of additional function during a refresh operation in a semiconductor memory device

A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.

Method and apparatus for programming non-volatile data storage device

A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of the memory devices and address/command or data termination information to a mode register of the corresponding memory device, and controlling resistances of ODT resistors of the signal lines in the memory devices in response to the address/command or data termination information and termination addresses. When only one of the memory devices is activated, ODT resistors of the activated memory device are set to a first resistance. When all the memory devices are activated, ODT resistors of the memory devices are set to a second resistance.

Growing community of inventors

Suwon-si, South Korea

Dong-woo Lee