Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Samsung Display Co., Ltd.

Samsung Corning Co., Ltd.

Samsung Sdi Co., Inc.

Boo Kang Tech Co., Ltd.

Filtech Korea Co., Ltd.

Dong-Woo Kim

Dong-Suk Shin

Dong-Min Kim

Kyoung Back Lee

Kyung-Joon Kwon

Gi-Gwan Park

Song-Ho Yoon

Songho Yoon

Shigenobu Maeda

Jung-Hwan Lee

Jeong-Woo Park

Hong-Sik Yoon

Kwan-heum Lee

Kang-Moon Jo

Young-Moon Choi

Do-Sun Lee

Sun-Woo Lee

Song Ho Yoon

Hyae-Ryoung Lee

Young-Ho Kim

Jin-Woo Kim

Hyoung-Kyu Lim

Jung-hyun Lee

Yong Chang

Sang-Yu Lee

Byung-sun Ahn

Hyeon-Yong Jang

Il-Gon Kim

Dongin Kim

Kyung-Hoon Kim

Dong-Keon Kong

Jae-Hee Oh

Joong-Hyun Kim

Nae-Hyun Lim

Jung-Hyeon Kim

Seung-hun Lee

An-Su Lee

Se-Hyoung Cho

Woong-Il Choi

Jung-gee Baek

Dong-Chan Suh

Hee-Won Ahn

Wook Han Jeong

Jae Sun No

Wook-Han Jeong

Seong-Ho Moon

Kwang-sung Hwang

Chang-Woo Sohn

Hyun-ho Noh

Yong-Bum Kwon

Sun-Il Yu

Yong-seung Kim

Yu-yeong Jo

Ki-Yeon Lee

Jin-Seob Byun

Jun-Hyun Park

Hyun-jung Lee

Min-Gyu Kim

Edward Namkyu Cho

Kyung-woo Lee

Hee-Jung Hong

Sun-jung Kim

Jung-Hoon Seo

Kwang-Hyeon Lee

Do-young Kim

Subramanya Mayya

Si-Hoon Lee

Kyo-Hyuck Choo

Byung June Song

Youngjoon Jang

Young-ran Kim

Xiaofeng Wang

Il-Gi Jeong

A-Rang Lee

Seok-Hyun Cho

Seog-Hyun Cho

In-Cheol Park

Jong-Seok Lee

Wookhan Jeong

Jeong-Je Park

Chang-Kyun Park

Hae-Soo Ha

Sung-Hak Jo

Gi Taek Park

Keum-seok Park

Jae-Hyeon Ko

Sang Wook Kim

Nam-Wook Jo

Ung-Gi Lee

Ha-Na Jung

Dai-Woong Choi

Yung-Hyun Lee

A display device including a substrate, a first upper power line, a conductive member, a protective insulating layer, an upper connection member, and a sub-pixel structure. The upper connection member is disposed in a first pad area and a first peripheral area on a planarization layer, and electrically connects the first upper power line and the conductive member through a first contact hole, which is formed in the protective insulating layer and the planarization layer located on the conductive member, and a second contact hole, which is formed in the protective insulating layer and the planarization layer located on the first upper power line.

Display device including conductive member electrically connected to power line

A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.

Storage device, memory system comprising the same, and operation method thereof

A method of operating a storage device includes receiving, at the storage device, a meta information transfer command based on a data read request. The meta information transfer command is received from a host device. The method further includes receiving, at the storage device, a data read command corresponding to the data read request and the meta information transfer command. The data read command is received from the host device. The method further includes receiving, at the storage device, a plurality of meta data corresponding to the data read request and the meta information transfer command. The plurality of meta data is received from the host device. The method further includes performing a data read operation, at the storage device, based on the data read command and the plurality of meta data.

Method of operating storage device, storage device performing the same and method of operating storage system using the same

A memory device, a host device and a memory system are provided. The memory device may include a plurality of storage units configured to store data, and at least one device controller configured to, receive a read command from at least one host device and to read data stored in the plurality of storage units in response to the read command, the at least one host device including at least one host memory including a plurality of HPB (high performance boosting) entry storage regions, and provide the at least one host device with a response command, the response command indicating an activation or deactivation of the plurality of HPB entry storage regions, the response command including HPB entry type information which indicates a HPB entry type of the HPB entry storage region.

Memory device, host device and memory system comprising the memory device and host device

A storage device includes a descramble module configured to descramble at least a portion of a read command, which includes logical block address (LBA) information and first meta information, into first signature information and first physical address (PA) information, for accessing a flash memory. A compare module is provided, which is configured to compare the first signature information against stored signature information to thereby determine an equivalency or discrepancy therebetween. An access module is provided, which is configured to use the first PA information to access a data region of the flash memory, upon determination of the equivalency by said compare module.

Storage devices that support cached physical address verification and methods of operating same

A memory system includes a storage device including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device, and a host that accesses the storage device. The storage device transfers map data, in which a physical address of the nonvolatile memory device and a logical address provided from the host are mapped, to the host depending on a request of the host. The host stores and manages the transferred map data as map cache data. The map cache data are managed depending on a priority that is determined based on a corresponding area of the nonvolatile memory device.

Storage device, memory system, and operating method for managing host-resident L2P map cache

A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Semiconductor device

A display apparatus in which each unit pixel includes four sub-pixels is provided. The four sub-pixels of each unit pixel may sequentially receive a data line through single data line. Two sub-pixels disposed on a side of the data line may be connected to a reference voltage supply line by a reference connecting line intersecting the data line. Two sub-pixels disposed another side of the data line may be connected to the data line by a data connection line intersecting the reference voltage supply line. An intersection region of the reference connection line and the data line may have the same area as an intersection region of the data connection line and the reference voltage supply line. Thus, in the display apparatus, the variation in the charging rate due to the parasitic capacitance difference of the data connection line and the reference connection line may be reduced.

Display apparatus having a unit pixel composed of four sub-pixels

Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8&#xd7;10/cmor more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7&#xb0; with a top surface of the fin structure.

Semiconductor device having a fin structure and a manufacturing method thereof

Multigate metal-oxide semiconductor field effect transistor

Growing community of inventors

Seoul, South Korea

Dong-Woo Kim