Samsung Electronics Co., Ltd.

Kt Corporation

Itx Security Co., Ltd.

Dong-Uk Park

Seok-Young Kong

Seong-Hee Suh

Jae-Seon Jang

Jin-Ho Seo

Jae-Jin Park

Tae-Pyeong Kim

Sang-Woo Pae

Han-Kyul Lim

Phil-Jae Jeon

Da Rae Ahn

Song-Nam Bae

Hye-Won Shim

Byung-Yun Lee

A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

Clock switch device and system-on-chip having the same

The present invention relates to an integrated repeater and an integrated relay system. The integrated repeater of the present invention receives a signal from a main repeater for relaying signals transmitted from upper devices, and comprises a demultiplexer configured to demultiplex the multiplexed signal of an Ethernet signal and a mobile communication signal received from the main repeater, and separate the signals into the mobile communication signal and the Ethernet signal; a first converter configured to convert the mobile communication signal separated from the demultiplexer into a radio frequency (RF) signal, and transmit the converted RF signal; a second converter configured to convert the Ethernet signal separated from the demultiplexer into a wireless LAN signal, and transmit the converted wireless LAN signal; and a switching unit configured to deliver a signal received from the main repeater to either the demultiplexer or the second converter, depending on whether a fault of the mobile communication signal is generated.

Integrated repeater for integratedly relaying various types of communication signals, and integrated relay system

A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Apparatus for frequency compensation using two counters

A network switch control digital video recorder (DVR) is provided. The network switch control DVR includes a network switch module configured to include a plurality of ports via which data is input to or output from at least one camera, a network storage, an external computer, and a DVR module and to multiplex data input or output via the plurality of ports; and the DVR module configured to control the input or output of data to or from the network switch module by monitoring a state of the input or output of data via the plurality of ports.

Network switch control digital video recorder

A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n&#x2212;1]) within the embedded clock data signal.

Display device transferring data signal with clock

A driver may include a plurality of data output units and/or a multi-phase clock generator. The plurality of data output units may be configured to output data based on a plurality of clock signals. The multi-phase clock generator may be configured to receive a master clock signal to generate the plurality of clock signals having different phases in a period of the master clock signal and/or to provide the clock signals to the data output units. A number of the clock signals may correspond to a number of the data output units.

Driver for reducing a noise, display device having the driver, and method thereof

A duty cycle correction circuit apparatus includes a flip-flop, a feedback unit connected between an input node and an output node of the flip-flop to invert an output signal of the flip-flop and to output the inverted signal as an output signal of the feedback unit, and a selection unit to select and output one of a first clock signal and a second clock signal to the flip-flop in response to the output signal of the feedback unit, wherein the first clock signal has a half-period phase difference with respect to the second clock signal. Using clock signals with a half-period phase difference therebetween and a simple digital circuit, the duty cycle correction circuit can correct a duty ratio to 50:50 regardless of an initial condition.

Duty cycle correction circuit apparatus

A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals.

Level shifting circuits for generating output signals having similar duty cycle ratios

A current drive circuit includes a differential voltage detector configured to detect a voltage level of a drive node and configured to compare the voltage level of the drive node with a voltage level of a reference voltage to generate a comparison signal, a control logic circuit configured to generate a control signal to provide a current to the drive node based on the comparison signal, and a current driver configured to provide the current to the drive node or provide the current from the drive node based on the control signal. The voltage level of the drive node rapidly reaches the voltage level of the reference voltage.

Current drive circuit and method of boosting current using the same

A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.

Current mode bus interface system, method of performing a mode transition and mode control signal generator for the same

A current driver circuit includes a pull-down switch unit that is coupled between a node and a first reference potential and is operative to switch between an on-state and an off-state responsive to an input signal. A pull-up switch unit is coupled between the node and a second reference potential and is operative to switch between an on-state and an off-state, complementary to the pull-down switch unit. A turn-on speed of the pull-up switch unit is slower than that of the pull-down switch unit, and a turn-off speed of the pull-up switch unit is faster than that of the pull-down switch unit.

Growing community of inventors

Gyeonggi-do, South Korea

Dong-Uk Park