Skhynix Inc.

Hynix Semiconductor Inc.

Hyundai Motor Company

Kia Motors Corporation

Samsung Sdi Co., Inc.

Generoath Co., Ltd

Lg Electronics Inc.

Korea University Research and Business Foundation

Korea Atomic Energy Research Institute

Korea Hydro Nuclear Power Co., Ltd.

Iksung Co., Ltd.

Korea Engineering Plastics Co., Ltd

Sun Jin Industry Co., Ltd.

Dong Uk Lee

Hae Chang Yang

Hun Wook Lee

Won Jin Seo

Kyung Whan Kim

Sung Chul Lee

Chan Ho Lee

Ju Yong Kim

Dong Kyun Kim

Dong Myung Suh

Min Su Park

Ji Hwan Kim

Sung Hyun Lee

Heat Bit Park

Young Ju Kim

Soon Joon Jung

Shin Deok Kang

Jin Kwang Kim

Jin Goo Ahn

Ji Yeon Yang

Jae Hyuk Bang

Jin Woo Choi

Dong Ha Jung

Dae Suk Kim

Dong Yun Lee

Seung Gyu Jeong

Su Nam Lee

Sang Jun Kong

Myeong Ju Ha

Ki Hwan Eum

Choung Ki Song

Jin Ho Hwang

Kyung Min Kim

Jung Wook Lee

Keun Young Kim

Jae Young Lee

Geun Ho Choi

Min Su Kim

Jin Hong An

Jae Wook Kwon

Kie Youn Jeong

Sang Keun Lee

Kwan Weon Kim

Bong Hyun Park

Seung Geun Baek

Seong Je Kim

Leonid Gorobinskiy

Se Chang Park

Seung Han Oak

Jae Beom Park

Yong Bum Lee

Oh Deok Kwon

Hyeon Ho Kim

Hak Song Kim

Ki Dong Lee

Ho Gyu Yoon

Ki Wook Yang

Seong Jin An

Gi Won Kim

Jae Hyuk Eoh

Man Seok Han

Kwang Myoung Rho

Yeong Chan Eun

Jae Hyung Park

Woo Yeong Cho

Kwon Yong Choi

Yong Kul Lee

Byung Guk Lim

Il Gon Lee

Hae Yong Jeong

Heun Young Seo

Yun Cheol Kim

Bong Joo Park

Yong Sik Yeom

Jae Won Moon

Moon Soo Lim

In Hee Song

Chungho Cho

Kwi Seok Ha

A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.

CMOS device, method of manufacturing CMOS device, and semiconductor memory device including CMOS device

There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.

Memory device and operating method of the memory device

A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Stacked integrated circuit

The present disclosure provides a chip including an even area including an even through via through which an even address is received and an even redundancy through via through which an even redundancy address is received, and an odd area including an odd through via through which an odd address is received and an odd redundancy through via through which an odd redundancy address is received. In the present disclosure, the even area may include an even address selection circuit configured to, based on a chip information signal, generate a selection even address and a selection even redundancy address from the even address, the even redundancy address, the odd address, and the odd redundancy address, and an even internal address generation circuit configured to, based on an even repair signal, generate an internal even address from the selection even address and the selection even redundancy address.

A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.

Semiconductor memory device and operating method of the semiconductor memory device

A switching element comprising: a first gate dielectric layer formed over a substrate; a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a second gate electrode formed over the second gate dielectric layer; and a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance.

Switching element

Provided is a pharmaceutical composition for preventing or treating neuronal diseases comprising, as an active ingredient, an exon 2-deleted AIMP2 variant (AIMP2-DX2) gene or a vector comprising the gene, and a method for treating neuronal diseases in animals other than humans, comprising administering the same to a subject in need of treatment. The pharmaceutical composition comprising, as an active ingredient, a AIMP2-DX2 gene or a vector comprising the gene has the effects of apoptosis inhibition, dyskinesia amelioration and oxidative stress inhibition and thus can be widely used for preventing and treating neuronal diseases such as Parkinson's disease and amyotrophic lateral sclerosis.

Pharmaceutical composition comprising AIMP2-DX2 for preventing or treating neuronal diseases and use thereof

A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.

Stacked semiconductor device

A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

Memory system and data processing system including the same

Switching element, semiconductor memory device including switching element, and method for fabricating the semiconductor memory device

A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Semiconductor memory device and methods of manufacturing and operating the same

The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.

Memory controller and operating method thereof

A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.

Semiconductor device and manufacturing method of semiconductor device

There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a plurality of memory blocks each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit for performing a general operation including a program operation, a read operation, and an erase operation on the plurality of memory blocks; and a control logic for controlling the peripheral circuit to operate in a heating mode in which the peripheral circuit applies heat to the plurality of memory blocks.

Semiconductor memory and operating method thereof

A memory controller that controls a memory device including a memory block includes an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block, a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block, and a pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines.

Memory controller and method of operating the memory controller

Growing community of inventors

Seoul, South Korea

Dong Uk Lee