Skhynix Inc.

Dong Uc Ko

Min Gu Kang

Dong Keun Kim

Jun Hyun Chun

Hyun Ju Yoon

Young Su Oh

Chang Kyu Choi

Hae Kang Jung

Tae Jin Hwang

Jun Yong Song

Sun Ki Cho

Yang Ho Sur

Sung Gil Jang

Min Sung Cheon

A memory module includes a module substrate, a plurality of memory devices, a first power line, and a second power line. The memory devices are mounted on the module substrate. Each of the memory devices includes a power management member. The first power line may be arranged in the module substrate to provide each of the memory devices with power. The second power line may be electrically connected between the power management members of adjacent memory devices to control and share the power provided to the adjacent memory devices.

Memory module including power line for supplying power to memory devices

A semiconductor apparatus includes a temperature detecting circuit and a temperature raising circuit. The temperature detecting circuit detects a temperature to generate temperature detection information. The temperature raising circuit generates heat through a toggling operation based on the temperature detection information.

Semiconductor apparatus and semiconductor memory apparatus

A memory system is provided to include a storage device including memory cells for storing data, and a controller in communication with an external device and configured to control the storage device based on a request from the external device. The controller is configured to receive a request from the external device to perform a refresh operation of re-writing stored data in the memory cells, read data from the memory cells included in the storage device, set a refresh period based on a number of fail bits included in the read data and a temperature of the controller or the storage device, and perform the refresh operation of the storage device based on the refresh period.

Controller and memory system for refreshing memory based on fail bits and temperature

There are provided a volatile memory device, and an operating method. The volatile memory device includes: a plurality of memory cells arranged in rows and columns and structured to store data; word lines; bit lines; a row decoder; a column decoder; and a control logic coupled to communicate with the row and column decoders and configured to, in an active period, provide the row decoder with a first command, and provide the column decoder with a second command, wherein the row decoder is further configured to: apply a first word line voltage higher than a ground voltage to a selected word line, from when the first command is provided; and for a duration over which the row decoder is activated, apply either a second word line voltage lower than the first word line voltage to the selected word line or no voltage to the selected word line.

Volatile memory device, storage device, and operating method of decreasing a leakage current

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

Buffer circuit

A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.

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Icheon-si, South Korea

Dong Uc Ko