Samsung Electronics Co., Ltd.

Dong-Sun Min

Soo-In Cho

Dae-Je Jin

Hoon Moo Choi

Chang-Hyun Kim

Dae-je Chin

Hong-sun Hwang

Yong-Sik Seok

Dong-soo Jun

Dong-Il Shu

Young-Rae Kim

Jae-Gu Roh

Su-In Cho

A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so as to reduce the power consumptions. The semiconductor memory device includes a block selector for selecting one of the main blocks in response to row address signals, a number of first boost circuits for selecting the subblocks of the selected main block in response to the row address signals, and a number of second boost circuits adapted to be disabled in response to the row address signals.

Semiconductor memory device having a block selection function with low

The higher packing cells memory circuit includes a plurality word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers by, for example, arranging word lines in a group to provide a cross-over or to twist the word line is not continuously adjacent to the same neighboring word line, so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

Method for reducing coupling noise of word lines in a semiconductor

A supply voltage converter circuit for use in reduced geometry high-density semiconductor memory devices, capable of reducing current consumption to as small a value as possible and achieving high-speed operation. The circuit includes a reference voltage generator, for generating a constant reference voltage, and a peripheral power-supply circuit, and array power-supply circuit for providing the internal supply voltage to the peripheral and array circuits, respectively. Each of the peripheral and array power circuits includes a divider, generating a voltage proportional to said internal supply voltage; a main power-supplying part including a main differential amplifier which compares the proportional voltage with said reference voltage and is activated by a given pulse, and a main power component providing the internal source supply voltage in response to output signal of the main differential amplifier; and a sub power supply part including a sub differential amplifier comparing the proportional voltage with the reference voltage, the differential amplifier being at a constant activation state, and a sub power component providing the internal source supply voltage in response to output signal of the sub differential amplifier.

Supply voltage converter for high-density semiconductor memory device

A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise. The bias circuit is connected to a clamping circuit having a comparator circuit to clamp the active restore voltage of the sense amplifier driving circuit, so that the active restore voltage can be maintained at the level of an internal voltage (approximately 4V), thereby preventing the distortion of the characteristics of the cell device and eliminating the necessity of additional standby current by enabling the sense amplifier only for the active restore operation. Further, the sense amplifier driving circuit comprises a constant circuit including two or more current mirror circuits which are sequentially activated, whereby the sense amplifier driving signals are made to have stable linear dual slopes.

Sense amplifier driving circuit employing current mirror for

A higher packing of cells in a memory circuit includes a plurality of word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

Interdigitated and twisted word line structure for semiconductor memories

An internal voltage converter in semiconductor integrated circuit, comprises an oscillator, a sub circuit including a buffer and a charge-pumping circuit and a power part, a main circuit including a buffer and a charge-pumping circuit and a power part, and a detector. A plurality of voltage converting stages are composed in parallel to be divided when operating so that the unnecesary consumption of the power is reduced in the case of providing the stand-by power and the stability of the internal power supply voltage is also improved.

Internal voltage converter in semiconductor integrated circuit

A semiconductor substrate bias circuit is disclosed which comprises: first and second substrate biasing means connected in parallel between the substrate and a ground node, for pumping the charges from said substrate to said ground node or in the reverse direction in order to bias said substrate; and a detecting means for selectively enabling said first and second substrate biasing means in accordance with the levels of the substrate bias voltage. The circuit of the present invention is capable of supplying adequate bias voltages depending on the various operating modes, reducing the standby current loss at a standby state, and is suitable for being installed on a VLSI semiconductor chip.

Semiconductor substrate bias circuit

A circuit for generating a back bias voltage for use in a semiconductor memory device is disclosed, wherein the back bias voltage is clamped within a desired voltage level. The circuit comprises an oscillator for generating a sequence of square waves having a specified frequency, a buffer adapted to be connected with the output of said oscillator and for buffering the output of said oscillator into the square waves having a level of a source supply voltage, a charge pump circuit for providing a back bias voltage by receiving the output of said buffer, and a clamping circuit adapted to be coupled in parallel between the output of said charge pump circuit and a ground level and for clamping within a specified range the back bias voltage being provided by said charge pump circuit in accordance with variations of said source supply voltage.

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Seoul, South Korea

Dong-Sun Min