Skhynix Inc.

Dong Sop Lee

Ie Ryung Park

Hyun Sub Kim

Sung Yeob Cho

Joung Young Lee

Youn Won Park

Tae Ho Lim

Dong Yeob Chun

Jae Min Jang

Wan Je Sung

Bo Seok Jeong

In Jae Yoo

A phase-change memory controller controls a phase-change memory device. The phase-change memory controller includes a write control circuit configured to receive first write data of 'N' bits (where “N” is a natural number greater than 2) to be written to the phase-change memory device to generate second write data composed of compressed data compressed with “M” bits (where “N” is a natural number smaller than “N”) and “0” padding data in which the rest “N-M” bits are filled with “0”.

Phase-change memory controller capable of reducing write power and phase-change memory system including same

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Memory controller and operating method thereof

A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.

Storage device for storing write data or reading read data and electronic device including the same

A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

Memory controller including memory manager for mapping buffer identifier to segment

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

The present disclosure relates to a semiconductor memory device including various types of memories to which a host is connected. The semiconductor memory device in one implementation includes a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory; a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory; and an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory.

Semiconductor memory device

A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.

Data coding device, memory controller, and storage device

A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.

Storage device for determining memory cell type after data input during program operation and operating method thereof

A storage device includes a memory device including one or more memory blocks including first sub-areas and second sub-areas configured to store higher level data than the first sub-areas, and a controller configured to use the first sub-areas before the second sub-areas in order to store data in the memory device.

Storage device

There are provided a controller, an electronic system including the same, and an operating method of the controller and the memory system. The controller includes: a randomizing circuit configured to generate random data having a set number of bits; a masking circuit configured to output select random data by extracting some data according to a number of bits on which a partial encoding operation is to be performed, among the random data; an operating circuit configured to output encoded data and a portion of original data, by performing an operation sequentially on the original data and the select random data; and a cyclic redundancy check circuit configured to generate a cyclic redundancy check value by performing a cyclic redundancy check on the encoded data and the portion of original data, and output partially encoded data including the cyclic redundancy check value, the portion of original data, and the encoded data.

Controller and operating method thereof

A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.

Memory system having memory controller

The present technology relates to an electronic device. More specifically, the present technology relates to a memory device, a storage device, and a method of operating a memory controller. According to an embodiment, a memory device that outputs read data in response to a read enable signal provided from a memory controller includes a plurality of memory cells configured to store data, a plurality of page buffers configured to sense the data stored in the plurality of memory cells through a plurality of bit lines, and a data output controller configured to select a target page buffer to output data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller and control the selected target page buffer to output data stored in the selected target page buffer according to the read enable signal, while the read enable signal is input.

Growing community of inventors

Gyeonggi-do, South Korea

Dong Sop Lee