Sungkyunkwan University

Dong Soo Lee

Kang Yoon Lee

Sang Yun Kim

Young Jun Park

Seong Jin Oh

In Seong Kim

A clock and data recovery circuit is disclosed herein. The clock and data recovery circuit includes a phase detection unit, a charge pump, a loop filter, a voltage control oscillator, and a frequency detection unit. The voltage control oscillator has oscillation frequency that is variable in response to a frequency adjustment signal, and outputs an oscillation signal. The frequency detection unit includes a reference clock divider, a counter, and an oscillation frequency control unit. The reference clock divider generates a count-enable signal based on a reference clock signal. The counter generates an oscillation count signal by counting the pulses of the oscillation signal of the voltage control oscillator or the pulses of divided signals resulting from dividing the oscillation signal while the count-enable signal is being enabled. The oscillation frequency control unit compares a target count value with the value of the oscillation count signal, and outputs the frequency adjustment signal.

Clock and data recovery circuit using digital frequency detection

An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.

Growing community of inventors

Dangjin-si, South Korea

Dong Soo Lee