Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Dong-Soo Kang

Eun-jin Ryu

Sung-Hyun Lee

Chul-woo Park

Young-Soo Sohn

Hak-soo Yu

Jae-Youn Youn

Su-a Kim

Hyo-jin Choi

Kyoung-june Min

Jun-Hee Yoo

Jong-myon Kim

Kyoung-Heon Jeong

Jae-young Lim

In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Memory system for continuously mapping addresses of a memory module having defective locations

A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request blocks and Arrival Times (ATs) of the DMA request signals, counting the number of priority changes of each of DMA request blocks whose priority is changed in the priority granting process, and if a DMA request signal is received from a new DMA request block, determining priorities of the DMA request blocks based on the counted the number of priority changes.

Method and apparatus for determining priorities in direct memory access device having multiple direct memory access request blocks

In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal. During the internal data transmission operation, the transmission data is transmitted from the region corresponding to the source address to a region corresponding to the target address, and is not output external to the semiconductor memory device.

Semiconductor memory device and internal data transmission method thereof

An image interpolation method interpolating image information of a point in a space constructed by a plurality of planes. According to the method, a reliable interpolated value can be rapidly obtained by searching for the nearest plane to the point, obtaining information about a plane facing the nearest plane using image information of one or more vertices of the plane facing the nearest plane, and interpolating the image information of the point using the image information of the one or more vertices of the nearest plane and the obtained information about the plane facing the nearest plane.

Image interpolation method, medium and system

Growing community of inventors

Hwaseong-si, South Korea

Dong-Soo Kang