Samsung Electronics Co., Ltd.

Dong-Seon Min

Yong-sik Seok

Dong-su Jeon

Dong-Soo Jeon

Kyoung-Yeol Min

A reference voltage generating circuit of a semiconductor memory device including a reference voltage circuit for producing a constant voltage, a differential amplifier for receiving the constant voltage as one input, a MOS transistor with the gate connected to the output of the differential amplifier and with the channel connected between a power supply terminal and a reference voltage output terminal and a voltage divider with an input and output respectively connected to the reference voltage output terminal and the other input of the differential amplifier, is disclosed. The voltage divider has a MOS transistor connected between the reference voltage output terminal and the output and a resistor connected between the output and ground voltage terminal, the MOS transistor being operated in saturation region. The voltage of the reference voltage output terminal is proportional to the constant voltage and inversely proportional to the resistance of the load means, to thereby keep a stable voltage regardless of the variation of the temperature and in manufacturing.

Reference voltage generating circuit of a semiconductor memory device

An arrangement of a word line driver stage for semiconductor memory device is disclosed. The present invention is characterized in that a word line driver stages are into several sub-stages WD11-WD51 within a memory cell array, and each word line extending from a first one or a second one of the sub-stages is alternatively coupled to the sub-stage adjacent thereto. Thus this arrangement is capable of reducing the signal transmission delay and eliminating the adverse factor in the current critical design rule and layout.

Arrangement of word line driver stage for semiconductor memory device

A method for making a sense amplifier capable of achieving high-speed sensing operation as well as incurring less influence from electrostatic capacitance of bit lines in a high-integration semiconductor memory (DRAM) device is disclosed. The DRAM device includes a plurality of word line pairs and bit line pairs, and a plurality of memory cell arrays with a plurality of memory cells, and further includes discrete sense amplifier circuits connected to each of the memory cell arrays, common sense amplifier circuits coupled between the discrete sense amplifiers, and separation circuits controlled by a given control signal and connected between the discrete sense amplifier circuits and common sense amplifier circuits.

Growing community of inventors

Seoul, South Korea

Dong-Seon Min