Samsung Electronics Co., Ltd.

Dong-Seok Suh

Yoon-Ho Khang

Tae-Sang Park

Ki-joon Kim

Kyoung-won Na

Eun-hong Lee

Deok-kee Kim

Young-kuk Kim

Mi-Lim Park

Matthias Wuttig

In Kyeong Yoo

Daniel Wamwangi

Tae-Seong Park

Kwnag-Soo Seol

Hori Ihideki

Wil-Liam Jo

Jin-Seo Noh

A storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change layer, and having different conductivity types. An upper surface of the lower electrode may have a recessed shape, and a lower electrode contact layer may be provided between the lower electrode and the phase change layer.

Storage node, phase change memory device and methods of operating and fabricating the same

A resistive memory device includes a vertical transistor and a variable resistance layer. The vertical transistor includes a gate electrode on a surface of a substrate, a gate insulation layer extending along a sidewall of the gate electrode, and a single crystalline silicon layer on the surface of the substrate adjacent to the gate insulation layer. At least a portion of the single crystalline silicon layer defines a channel region that extends in a direction substantially perpendicular to the surface of the substrate. The variable resistance layer is provided on the single crystalline silicon layer. The variable resistance layer is electrically insulated from the gate electrode. Related devices and fabrication methods are also discussed.

Resistive memory devices including vertical transistor arrays and related fabrication methods

A method of measuring a resistance of a memory cell in a resistive memory device can be provided by applying a data write pulse to a selected cell of the resistive memory device, applying a resistance read pulse to the selected cell after a delay time measured from a time of applying the data write pulse, measuring a drop voltage at the cell responsive to a pulse waveform output when applying the resistance read pulse to the selected cell, measuring a total current through the cell using the drop voltage and an internal resistance of a test device coupled to the cell, and determining a resistance of the resistive memory device using the total current and a voltage of the resistance read pulse.

Method of measuring a resistance of a resistive memory device

A storage node, a phase change memory device, and methods of operating and fabricating the same are provided. The storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change layer, and having different conductivity types. An upper surface of the lower electrode may have a recessed shape, and a lower electrode contact layer may be provided between the lower electrode and the phase change layer. A thickness of the phase change layer may be about 100 nm or less, and the lower electrode may be composed of an n-type thermoelectric material, and the upper electrode may be composed of a p-type thermoelectric material, or they may be composed on the contrary to the above. Seeback coefficients of the lower electrode, the phase change layer, and the upper electrode may be different from each other.

Provided are a doped phase change material and a phase change memory device including the phase change material. The phase change material, which may be doped with Se, has a higher crystallization temperature than a GeSbTe(GST) material. The phase change material may be InSbTeSe. The index X of indium (In) is in the range of 25 wt %&#x2266;X&#x2266;60 wt %. The index Y of antimony (Sb) is in the range of 1 wt %&#x2266;Y&#x2266;17 wt %. The index Z of tellurium (Te) is in the range of 0 wt %&#x3c;Z&#x2266;75 wt %.

Doped phase change material and pram including the same

A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may include a switching device and the storage node. The switching device may be connected to the bottom electrode contact layer. A method of manufacturing the storage node may include forming a via hole in an insulating interlayer, at least partially filling the via hole to form a bottom electrode contact layer, protruding the bottom electrode contact layer from the via hole, and forming a phase change layer that covers the bottom electrode contact layer. A method of manufacturing a phase change memory device may include forming the switching device on a substrate and manufacturing the storage node.

Storage nodes, phase change memory devices, and methods of manufacturing the same

A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.

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Yongin-si, South Korea

Dong-Seok Suh