Samsung Electronics Co., Ltd.

Dong-ryul Ryu

Chi-wook Kim

Chang-sik Kim

Seok-Won Hwang

Hyun-Dong Kim

Young-uk Chang

An integrated circuit memory device includes a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and is configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device. Related methods are also disclosed.

Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device

Clock generating circuits for a semiconductor memory device are provided. The clock generating circuits include a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device. A control circuit activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self refresh mode, in which the DLL circuit is deactivated, to a standby mode. The control circuit may also be configured to deactivate the DLL circuit when the semiconductor memory device transitions from a power down mode, in which the DLL circuit is activated, to the standby mode. The semiconductor memory device may be a dynamic random access memory device and the predetermined time may be a number of clock cycles of the internal clock signal. Methods for operating the same are also provided.

Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same

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Kyounggi-do, South Korea

Dong-ryul Ryu