Hitachi Micro Systems, Inc.

Dong-Ru Shieh

Tsu-Wei Ku

Wei-Kong Chia

A logic simulation system and method reduces the number of events to be simulated. The simulator receives a user specified circuit netlist denoting a specified logic circuit's components and the nodes interconnecting those components. A user specified watched nodes list identifies the circuit nodes for which output waveforms are to be generated. A cell library provides cell delay data representing signal delays from each input port to each output port of each circuit component. A set of input signal waveforms are compiled into a sequence of variable length time periods and each input signal is assigned an extended boolean value for each time period. The extended boolean values identify signals that are stable over the time period, signals with a single transition during the time period, and signals with multiple transitions during the time period. For each time period, operation of the logic circuit is initially simulated without determining when signal transitions on the circuit's nodes occur, by performing an extended zero delay simulation. The extended zero delay simulation assigns to each circuit node an extended boolean signal value selected from the set consisting of stable signal values (0, 1, X and Z), signal values (t0, t1, tX, tZ) having a single transition during the time period, and a signal value (mt) indicating more than one transition during the time period. For each time period, the circuit is backtracked from those watched nodes assigned non-stable values so as to identify nodes that control those watched nodes and that were assigned non-stable values. Then event driven simulation of the logic circuit is performed for events on those identified nodes.

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Cupertino, CA, United States of America

Dong-Ru Shieh