Realtek Semiconductor Inc.

Dong Qiu

Xiang-Hua Shen

De-Pin Zheng

Meng Huang Liu

Jia-Jia Cai

Fei Yan

Zhi-Qiang Yang

Bin Chen

A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.

Verifying method for ECC circuit of SRAM

A chip verification system includes a plurality of agent modules, a register model, and a scoreboard module. The register model includes a register database, a plurality of access modules, and a return module. Each access module corresponds to one of a plurality of attribute parameters. Each agent module transmits an address code of its sequence to the return module. The return module obtains, according to the received address code, an address subject and the attribute parameter corresponding to the received address code from the register database, and outputs the obtained attribute parameter. Each driver module calls, according to the received attribute parameter, the corresponding access module to perform an operation on registers of DUT circuit according to a read write command of the sequence. The scoreboard module records each performed operation to generate an operation record, and outputs a verification result according to the operation record and data in registers.

Chip verification system and verification method therefor

A method of testing a slave device of an Inter-Integrated Circuit (IC) bus is provided. The method includes the following steps: (A) starting a first read operation or a first write operation of the slave device, the first read operation or the first write operation including a sub-operation of sending a command, an acknowledgement signal, data, an address or a control byte to the slave device; (B) sending a start command or an end command to the slave device after or during the sub-operation; (C) after step (B), performing a second read operation or a second write operation on the slave device; and (D) after step (C), determining whether the second read operation or the second write operation is correctly performed.

Method of testing slave device of inter-integrated circuit bus

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Hsinchu, Taiwan

Dong Qiu