Advanced Micro Devices Corporation

Calithera Biosciences, Inc.

Scaleflux, Inc.

Dong Ping Zhang

Nuwan S Jayasena

Alexander Dodd Breslow

Francesco Parlati

Yasuko Eckert

Indrani Paul

Manish Arora

Yang Liu

Yong Peng

Susanne M Steggerda

Jiangpeng Li

Paula Aguilera Diez

Melissa G Works

Mirna L M Rodriguez

Andrew L MacKinnon

Mirna L Rodriguez

A storage device that provides in-storage transparent compression and implements a process for processing write requests during an out-of-space state. The process includes: receiving a write request from a host involving a set of logical block addresses (LBAs); determining if each of the LBAs in the write request is an actively used LBAs; and in response to determining that each of the LBAs in the write request are actively used LBAs, allowing the write request to be served; and in response to determining that at least one of the LBAs in the write request is not an actively used LBAs, not allowing the write request to be served and returning an error to the host.

Techniques to enhance storage devices with built-in transparent compression for mitigating out-of-space issues

Methods and mechanisms for managing data in a hash table are disclosed. A computing system includes a hash table configured to store data and hash management logic. In response to receiving a request to insert data into the hash table, the hash management logic is configured to generate a first hash value by applying a first hash function to the key of the key-value pair, and identify a first bucket within the hash table that corresponds to the first hash table. If the first bucket has a slot available, store the key-value pair in the slot. If the first bucket does not have a slot available, select a first slot of the first bucket for conversion to a remap entry, store the key-value pair in a second bucket, and store information associating the key-value pair with the second bucket in the remap entry.

Bucketized hash tables with remap entries

A method and apparatus for performing a search in a processor-in-memory (PIM) system having a first processor and at least one memory module includes receiving one or more images by the first processor. The first processor sends a query for a search of memory for a matching image to the one or more images to at least one memory module, which searches memory in the memory module, in response to the received query. The at least one memory module sends the results of the search to the first processor, and the first processor performs a comparison of the received results from the at least one memory module to the received one or more images.

Method and apparatus for performing a parallel search operation

The invention relates to methods of treating lung cancer using glutaminase inhibitors. In particular, results demonstrate that lung cancers characterized by an EGFR or KRAS mutation are treated by glutaminase inhibitors.

Treatment of lung cancer with inhibitors of glutaminase

A cooling system is provided for a 3D integrated circuit (IC) to deliver fluid in x, y, and z dimensions to interior regions of the IC as a means to regulate heat. An IC includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (MEMS)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. Each sensor monitors a state of the IC. Each MEMS-based device receives control signals based on a state of the IC and regulates a flow of fluid within the network of channels based on control signals that area received on a real-time basis based on changes detected in a state of the IC.

Control system and architecture for incorporating microelectromechanical (MEM) switches in fluid-based cooling of 3D integrated circuits

A processing system includes a processing module having a first interface coupleable to an interconnect. The first interface includes a first cryptologic engine to encrypt a representation of store data of a store operation and a memory address using a first key and a first feedback-based cryptologic process to generate first encrypted data and an encrypted memory address. A memory module includes a second interface coupled to the interconnect. The second interface includes a second cryptologic engine to decrypt the first encrypted data and the encrypted memory address using a second key and a second feedback-based cryptologic process to generate a copy of the representation of the store data and a copy of the memory address. The second interface further is to store the copy of the representation of the store data to a memory location of the memory core based on the copy of the memory address.

Memory operation encryption

Systems, apparatuses, and methods for migrating execution contexts are disclosed. A system includes a plurality of processing units and memory devices. The system is configured to execute any number of software applications. The system is configured to detect, within a first software application, a primitive for migrating at least a portion of the execution context of a source processing unit to a target processing unit, wherein the primitive includes one or more instructions. The execution context includes a plurality of registers. A first processing unit is configured to execute the one or more instructions of the primitive to cause a portion of an execution context of the first processing unit to be migrated to a second processing unit. In one embodiment, executing the primitive instruction(s) causes an instruction pointer value, with an optional offset value, to be sent to the second processing unit.

Instruction set architecture and software support for register state migration

Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.

Efficient accesses of data structures using processing near memory

A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Thermal aware data placement and compute dispatch in a memory system

The invention relates to methods of treating cancer, myeloproliferative diseases, or immunological or neurological diseases with a combination of a glutaminase inhibitor and an anticancer agent such as an enzyme inhibitor (such as a kinase inhibitor), a mitotic inhibitor, a DNA-modifying agent, or a cytidine analog. The invention further relates to methods of treating cancer, myeloproliferative diseases, or immunological or neurological diseases that are resistant to one or more anticancer agents.

Growing community of inventors

Sunnyvale, CA, United States of America

Dong Ping Zhang