Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Dong-Min Shin

Hong Rak Son

Jun-Jin Kong

Kijun Lee

Junjin Kong

Kyeongcheol Yang

Geunyeong Yu

Myung-Kyu Lee

Kangseok Lee

Beom-Kyu Shin

Seung-Chan Lim

Wi Jik Lee

Hee Youl Kwak

Young Jun Hwang

Hong-Sil Jeong

Jae-Yoel Kim

Hyun-Koo Yang

Jun Jin Kong

Hong-Rak Son

Bohwan Jun

Jae Hun Jang

Myungkyu Lee

Eun-chu Oh

Youngjun Hwang

Min Uk Kim

Se Jin Lim

Heon Hwa Cheong

Hak-Ju Lee

Sung-ryul Yun

Se-Ho Myung

Kyeong-Cheol Yang

Changkyu Seol

Sung-Ryul Yun

Pil-sang Yoon

Sunghye Cho

Minuk Kim

Seonghyeog Choi

Ki Jun Lee

Kyung-Joong Kim

Beomkyu Shin

Beom Kyu Shin

Ki-Jun Lee

Jiyoup Kim

Seong Hyeog Choi

Se-jong Ko

Hyunseung Han

Tae Hyun Song

Eun-cheol Kim

Hyeonjong Song

Ung-hwan Kim

Heeyoul Kwak

Geun-Yeong Yu

Young Suk Ra

Yeongcheol Jo

Jaeyong Son

Jong-Ha Kim

Ji-Youp Kim

Hyeon-Koo Yang

Tae-Juon Kim

Seung-Ho Jun

Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.

Memory controller, storage device and operating method of memory controller

Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.

Operation method of memory controller configured to control memory device

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ioperation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ioperation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Decoder performing iterative decoding, and storage device using the same

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

Memory system including field programmable gate array (FPGA) and method of operating same

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Error correction circuit and method for operating the same

A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by 'k' states (k being an integer greater than 2) smaller in number than the 2states, performs first error correction encoding on the second write data to generate third write data expressed by the 'k' states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

Storage device that performs state shaping of data

An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

Operating method of memory controller, storage device and the operating method thereof

An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

Storage controller for correcting error, storage device including the same, and operating method thereof

An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

Memory controller, operating method of memory controller and memory system

An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate.

Error correction device, operating method of error correction device, and controller including error correction device

A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Method of recovering data and memory system and raid storage system using the same

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Seoul, South Korea

Dong-Min Shin