Skhynix Inc.

Hynix Semiconductor Inc.

Dong Kyun Kim

Min Su Park

Dong Uk Lee

Geun Ho Choi

Chang Hyun Kim

Jae Il Kim

Sang Sic Yoon

Bok Rim Ko

Sang Kwon Lee

Keun Soo Song

Dae Suk Kim

Jeong Jun Lee

Kyung Whan Kim

Hak Song Kim

Hoi Ju Chung

Jae Yung Jun

Yun Keuk Kim

Sungchun Jang

Su Chang Kim

An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.

Electronic device for performing data masking operation

A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.

Memory system

A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

Methods, controllers, and semiconductor systems for generating write commands

An electronic device may include an information signal storage circuit and a write data selection circuit. The information signal storage circuit may be configured to store an information signal during a mode register set operation, and may be configured to output the stored information signal as a mode register information signal. The write data selection circuit may be configured to receive the mode register information and output the mode register information signal as write data.

Electronic devices relating to a mode register information signal

A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Semiconductor apparatus, semiconductor system, and training method

A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code

A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.

Semiconductor device

An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. The locked clock generation circuit includes an oscillator and generates a locked clock signal for generating an internal clock signal from the interpolation clock signal.

Internal clock generation circuits

A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.

Semiconductor devices

A duty correction device may be provided. The duty correction device may include a duty controller configured to output a control signal by controlling a duty of a duty corrected signal, and detect a level of a feedback signal to convert the duty based on a code signal which is applied at a section where the level of the feedback signal corresponds to a logic level. The duty correction device may include a power gating circuit configured to generate the feedback signal by driving the control signal.

Duty correction device and semiconductor device including the same

Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. In addition, the semiconductor chip includes a third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction. Data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization. Related semiconductor chip packages and semiconductor systems are also provided.

Semiconductor chips, semiconductor chip packages including the same, and semiconductor systems including the same

A integrated circuit may include an input buffer suitable for buffering a strobe signal in response to a buffer enablement signal to generate an internal strobe signal, an internal clock generator suitable for receiving the internal strobe signal to generate internal clock signals including different phases. The integrated circuit may include a strobe signal driver suitable for driving the strobe signal in response to a drive control signal. The drive control signal may be enabled prior to the buffer enablement signal being enabled.

Integrated circuits and semiconductor systems including the same

A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage.

Growing community of inventors

Cheongju-si, South Korea

Dong Kyun Kim