Samsung Electronics Co., Ltd.

Yonsei University

Dong-Kwan Suh

Dae-Hyun Kim

Kyoung-Hoon Kim

Hyun-Jung Kim

Suk-jin Kim

Hyeong-Seok Yu

Tai-song Jin

Young-chul Cho

Ki-seok Kwon

Jae-un Park

Young-Hwan Park

Yen-Jo Han

Keshava Prasad Nagaraja

San Hae Kim

Yong-Surk Lee

Han-Su Cho

Jung-Uk Cho

A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

Reconfigurable processor and mini-core of reconfigurable processor

A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

Reconfigurable processor and reconfigurable processing method of vector operation using vector lane configuration information

A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

Verification supporting apparatus and verification supporting method of reconfigurable processor

A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

Fused multiply-add apparatus and method

Growing community of inventors

Hwaseong-si, South Korea

Dong-Kwan Suh