Samsung Electronics Co., Ltd.

Dong-Kwan Han

Ji-Hye Kim

Ju-Hee Han

Yo-Seop Lim

A repair information providing device in an integrated circuit including a plurality of memory blocks includes a plurality of faulty cell address registers connected to the memory blocks, respectively, a repair information storage block configured to store repair information including an address of a faulty cell and a memory index indicating a memory block having the faulty cell, a repair information control block configured to read the repair information from the repair information storage block, transfer the address of the faulty cell included in the repair information to the respective faulty cell address registers, and generate a memory block selection signal based on the memory index included in the repair information, and a clock gating block configured to receive a clock signal, and selectively transfer the clock signal to one of the faulty cell address registers connected to the memory block having the faulty cell in response to receiving the memory block selection signal.

Repair information providing device in an integrated circuit

A system on chip (SOC) is provided. The system on chip (SOC) includes: at least one core including a plurality of scan chains operated by a trigger signal; a delay controller generating a delay target selection signal selecting at least one of the plurality of scan chains and a delay depth control signal indicating a delay depth of the trigger signal; and a delay signal generating unit delaying the trigger signal based on the delay target selection signal and the delay depth control signal and providing the delayed trigger signal to the plurality of scan chains.

System on chip

A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains comprising unknown values which could adversely influence a test result. The test circuit uses a scan test point circuit to prevent unknown values from propagating through the test circuit, thus keeping the unknown values from influencing the test result. The reordering method is used where two scan chains comprising an unknown value exist in a single scan cycle so that the unknown values can be located during different clock cycles.

Scan based automatic test pattern generation (ATPG) test circuit, test method using the test circuit, and scan chain reordering method

A system on chip and method of testing and/or debugging the same, where the system on chip includes a plurality of circuits and a control circuit for receiving a serial-parallel mode control signal and at least one selection signal externally input from one or more of a plurality of pins and outputting an output signal depending on values of the serial-parallel mode control signal and the at least one selection signal.

Growing community of inventors

Suwon-si, South Korea

Dong-Kwan Han